From 3e42133abd472a5441727d741ea67508e5681a36 Mon Sep 17 00:00:00 2001 From: Christian Klarhorst Date: Tue, 30 Aug 2022 16:22:29 +0200 Subject: [PATCH] Change SDRAM region to RWX --- litex/soc/integration/soc.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 1c912e211..4e9a4b87c 100755 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1461,7 +1461,8 @@ class LiteXSoC(SoC): # Add SDRAM region. main_ram_region = SoCRegion(origin=self.mem_map.get("main_ram", origin), - size=sdram_size) + size=sdram_size, + mode="rwx") self.bus.add_region("main_ram", main_ram_region) # Add CPU's direct memory buses (if not already declared) ----------------------------------