From 3e77ae788fcfd028bd6e827b3e7e4ab84b82dcf2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 19 Sep 2018 19:19:50 +0200 Subject: [PATCH] targets: replace MiniSoC with EthernetSoC --- litex/boards/targets/arty.py | 4 ++-- litex/boards/targets/genesys2.py | 4 ++-- litex/boards/targets/kc705.py | 4 ++-- litex/boards/targets/nexys_video.py | 4 ++-- litex/boards/targets/simple.py | 4 ++-- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index aeda2f901..d8f3f8242 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -114,7 +114,7 @@ class BaseSoC(SoCSDRAM): sdram_module.timing_settings) -class MiniSoC(BaseSoC): +class EthernetSoC(BaseSoC): csr_map = { "ethphy": 18, "ethmac": 19 @@ -161,7 +161,7 @@ def main(): help="enable Ethernet support") args = parser.parse_args() - cls = MiniSoC if args.with_ethernet else BaseSoC + cls = EthernetSoC if args.with_ethernet else BaseSoC soc = cls(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 5702a5e23..3046ec4cf 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -96,7 +96,7 @@ class BaseSoC(SoCSDRAM): sdram_module.timing_settings) -class MiniSoC(BaseSoC): +class EthernetSoC(BaseSoC): csr_map = { "ethphy": 18, "ethmac": 19 @@ -143,7 +143,7 @@ def main(): help="enable Ethernet support") args = parser.parse_args() - cls = MiniSoC if args.with_ethernet else BaseSoC + cls = EthernetSoC if args.with_ethernet else BaseSoC soc = cls(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index c2d2553d6..65730af53 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -96,7 +96,7 @@ class BaseSoC(SoCSDRAM): sdram_module.timing_settings) -class MiniSoC(BaseSoC): +class EthernetSoC(BaseSoC): csr_map = { "ethphy": 18, "ethmac": 19 @@ -143,7 +143,7 @@ def main(): help="enable Ethernet support") args = parser.parse_args() - cls = MiniSoC if args.with_ethernet else BaseSoC + cls = EthernetSoC if args.with_ethernet else BaseSoC soc = cls(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 1af07c7f8..4f297deb1 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -103,7 +103,7 @@ class BaseSoC(SoCSDRAM): sdram_module.timing_settings) -class MiniSoC(BaseSoC): +class EthernetSoC(BaseSoC): csr_map = { "ethphy": 18, "ethmac": 19 @@ -150,7 +150,7 @@ def main(): help="enable Ethernet support") args = parser.parse_args() - cls = MiniSoC if args.with_ethernet else BaseSoC + cls = EthernetSoC if args.with_ethernet else BaseSoC soc = cls(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index 8577a04a1..de7cc60d8 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -22,7 +22,7 @@ class BaseSoC(SoCCore): self.submodules.crg = CRG(platform.request(platform.default_clk_name)) -class MiniSoC(BaseSoC): +class EthernetSoC(BaseSoC): csr_map = { "ethphy": 20, "ethmac": 21 @@ -62,7 +62,7 @@ def main(): platform_module = importlib.import_module(args.platform) platform = platform_module.Platform() - cls = MiniSoC if args.with_ethernet else BaseSoC + cls = EthernetSoC if args.with_ethernet else BaseSoC soc = cls(platform, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build()