From 3f095a260df420d1953bc4b99325a1873b6c0546 Mon Sep 17 00:00:00 2001
From: JoyBed <46244284+JoyBed@users.noreply.github.com>
Date: Sun, 16 Jun 2024 18:50:55 +0200
Subject: [PATCH] Fix HP slave clock source and specify AXI version

The absence of WID signal in AXI4 when compared to AXI3 can sometimes cause problems.
---
 litex/soc/cores/cpu/zynq7000/core.py | 27 ++++++++++++++++++++++-----
 1 file changed, 22 insertions(+), 5 deletions(-)

diff --git a/litex/soc/cores/cpu/zynq7000/core.py b/litex/soc/cores/cpu/zynq7000/core.py
index afd94559e..f053682d4 100644
--- a/litex/soc/cores/cpu/zynq7000/core.py
+++ b/litex/soc/cores/cpu/zynq7000/core.py
@@ -214,7 +214,12 @@ class Zynq7000(CPU):
     def add_axi_gp_master(self):
         assert len(self.axi_gp_masters) < 2
         n       = len(self.axi_gp_masters)
-        axi_gpn = axi.AXIInterface(data_width=32, address_width=32, id_width=12)
+        axi_gpn = axi.AXIInterface(
+            data_width    = 32,
+            address_width = 32,
+            id_width      = 12,
+            version       = "axi3"
+        )
         self.axi_gp_masters.append(axi_gpn)
         self.cpu_params.update({
             # AXI GP clk.
@@ -275,7 +280,13 @@ class Zynq7000(CPU):
     def add_axi_gp_slave(self, clock_domain="ps7"):
         assert len(self.axi_gp_slaves) < 2
         n       = len(self.axi_gp_slaves)
-        axi_gpn = axi.AXIInterface(data_width=32, address_width=32, id_width=12, clock_domain=clock_domain)
+        axi_gpn = axi.AXIInterface(
+            data_width    = 32,
+            address_width = 32,
+            id_width      = 12,
+            version       = "axi3",
+            clock_domain  = clock_domain
+        )
         self.axi_gp_slaves.append(axi_gpn)
         self.cpu_params.update({
             #AXI S GP clk.
@@ -333,14 +344,20 @@ class Zynq7000(CPU):
 
     # AXI High Performance Slave -------------------------------------------------------------------
 
-    def add_axi_hp_slave(self):
+    def add_axi_hp_slave(self, clock_domain="ps7"):
         assert len(self.axi_hp_slaves) < 4
         n       = len(self.axi_hp_slaves)
-        axi_hpn = axi.AXIInterface(data_width=64, address_width=32, id_width=6)
+        axi_hpn = axi.AXIInterface(
+            data_width    = 64,
+            address_width = 32,
+            id_width      = 6,
+            version       = "axi3",
+            clock_domain  = clock_domain
+        )
         self.axi_hp_slaves.append(axi_hpn)
         self.cpu_params.update({
             # AXI HP0 clk.
-            f"i_S_AXI_HP{n}_ACLK"    : ClockSignal("ps7"),
+            f"i_S_AXI_HP{n}_ACLK"    : ClockSignal(clock_domain),
 
             # AXI HP0 aw.
             f"i_S_AXI_HP{n}_AWVALID" : axi_hpn.aw.valid,