From 3f15699964e82054b4261a5100ce4fbce8a5e0dc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Apr 2015 21:47:55 +0200 Subject: [PATCH] revert fhdl/verilog: avoid reg initialization in printheader when reset is not an int. (sorry merge issue) --- migen/fhdl/verilog.py | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py index 4cc657b38..5d5f5896e 100644 --- a/migen/fhdl/verilog.py +++ b/migen/fhdl/verilog.py @@ -178,11 +178,7 @@ def _printheader(f, ios, name, ns): if sig in wires: r += "wire " + _printsig(ns, sig) + ";\n" else: - if isinstance(sig.reset, int): - resetexpr = " = " + _printexpr(ns, sig.reset)[0] - else: - resetexpr = "" - r += "reg " + _printsig(ns, sig) + resetexpr + ";\n" + r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n" r += "\n" return r