From 4050e608340c05228f89deacd04e22ca15ae72a8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 13 Jan 2020 20:01:45 +0100 Subject: [PATCH] SoCCore: use hex for integrated_rom/sram_size --- litex/soc/integration/soc_core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 59faef811..ffe0546fb 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -85,9 +85,9 @@ class SoCCore(Module): # CPU parameters cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None, # ROM parameters - integrated_rom_size=32768, integrated_rom_init=[], + integrated_rom_size=0x8000, integrated_rom_init=[], # SRAM parameters - integrated_sram_size=4096, integrated_sram_init=[], + integrated_sram_size=0x1000, integrated_sram_init=[], # MAIN_RAM parameters integrated_main_ram_size=0, integrated_main_ram_init=[], # CSR parameters