From 40c001d522d4c5446e6e2f903bbe4869c4a660dd Mon Sep 17 00:00:00 2001 From: Franck Jullien Date: Mon, 13 Dec 2021 14:42:33 +0100 Subject: [PATCH] check calculated PLL frequencies against user's values --- litex/build/efinix/ifacewriter.py | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/litex/build/efinix/ifacewriter.py b/litex/build/efinix/ifacewriter.py index 2eb6b8b70..4fed01f40 100644 --- a/litex/build/efinix/ifacewriter.py +++ b/litex/build/efinix/ifacewriter.py @@ -220,13 +220,19 @@ design.create("{2}", "{3}", "./../gateware", overwrite=True) cmd += 'print("#### {} ####")\n'.format(name) cmd += 'clksrc_info = design.trace_ref_clock("{}", block_type="PLL")\n'.format(name) cmd += 'pprint.pprint(clksrc_info)\n' - cmd += 'clock_source_prop = ["REFCLK_SOURCE", "CORE_CLK_PIN", "EXT_CLK", "CLKOUT1_EN", "CLKOUT2_EN","REFCLK_FREQ", "RESOURCE"]\n' - cmd += 'clock_source_prop += ["CLKOUT0_FREQ", "CLKOUT1_FREQ", "CLKOUT2_FREQ"]\n' - cmd += 'clock_source_prop += ["CLKOUT0_PHASE", "CLKOUT1_PHASE", "CLKOUT2_PHASE"]\n' + cmd += 'clock_source_prop = ["REFCLK_SOURCE", "CORE_CLK_PIN", "EXT_CLK", "REFCLK_FREQ", "RESOURCE"]\n' + for i, clock in enumerate(block["clk_out"]): + cmd += 'clock_source_prop += ["CLKOUT{}_FREQ", "CLKOUT{}_PHASE", "CLKOUT{}_EN"]\n'.format(i, i, i) cmd += 'prop_map = design.get_property("{}", clock_source_prop, block_type="PLL")\n'.format(name) cmd += 'pprint.pprint(prop_map)\n' - cmd += "# ---------- END PLL {} ---------\n\n".format(name) + for i, clock in enumerate(block["clk_out"]): + cmd += '\nfreq = float(prop_map["CLKOUT{}_FREQ"])\n'.format(i) + cmd += 'if freq != {}:\n'.format(clock[1]/1e6) + cmd += ' print("ERROR: CLKOUT{} configured for {}MHz is {{}}MHz".format(freq))\n'.format(i, clock[1]/1e6) + cmd += ' exit("PLL ERROR")\n' + + cmd += "\n#---------- END PLL {} ---------\n\n".format(name) return cmd def generate(self, partnumber):