From 410a16284120107027e503b439e3ac62a8c6fe51 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 2 Mar 2015 19:53:16 +0100 Subject: [PATCH] sdram: disable by default bandwidth_measurement on lasmicon --- misoclib/mem/sdram/core/__init__.py | 4 ++-- misoclib/mem/sdram/core/lasmicon/__init__.py | 5 +++-- misoclib/mem/sdram/core/lasmicon/multiplexer.py | 6 ++++-- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/misoclib/mem/sdram/core/__init__.py b/misoclib/mem/sdram/core/__init__.py index c4a5f9fbd..a46942b19 100644 --- a/misoclib/mem/sdram/core/__init__.py +++ b/misoclib/mem/sdram/core/__init__.py @@ -7,14 +7,14 @@ from misoclib.mem.sdram.core import minicon, lasmicon from misoclib.mem.sdram.core.lasmicon.crossbar import Crossbar class SDRAMCore(Module, AutoCSR): - def __init__(self, phy, ramcon_type, sdram_geom, sdram_timing): + def __init__(self, phy, ramcon_type, sdram_geom, sdram_timing, **kwargs): # DFI self.submodules.dfii = dfii.DFIInjector(phy, sdram_geom.mux_a, sdram_geom.bank_a) self.comb += Record.connect(self.dfii.master, phy.dfi) # LASMICON if ramcon_type == "lasmicon": - self.submodules.controller = controller = lasmicon.LASMIcon(phy, sdram_geom, sdram_timing) + self.submodules.controller = controller = lasmicon.LASMIcon(phy, sdram_geom, sdram_timing, **kwargs) self.comb += Record.connect(controller.dfi, self.dfii.slave) self.submodules.crossbar = crossbar = Crossbar([controller.lasmic], controller.nrowbits) diff --git a/misoclib/mem/sdram/core/lasmicon/__init__.py b/misoclib/mem/sdram/core/lasmicon/__init__.py index 5fdd38cda..2fc8f3a8a 100644 --- a/misoclib/mem/sdram/core/lasmicon/__init__.py +++ b/misoclib/mem/sdram/core/lasmicon/__init__.py @@ -6,7 +6,7 @@ from misoclib.mem.sdram.core.lasmicon.bankmachine import * from misoclib.mem.sdram.core.lasmicon.multiplexer import * class LASMIcon(Module): - def __init__(self, phy, geom_settings, timing_settings): + def __init__(self, phy, geom_settings, timing_settings, **kwargs): if phy.settings.memtype in ["SDR"]: burst_length = phy.settings.nphases*1 # command multiplication*SDR elif phy.settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]: @@ -35,7 +35,8 @@ class LASMIcon(Module): for i in range(2**geom_settings.bank_a)] self.submodules.multiplexer = Multiplexer(phy, geom_settings, timing_settings, self.bank_machines, self.refresher, - self.dfi, self.lasmic) + self.dfi, self.lasmic, + **kwargs) def get_csrs(self): return self.multiplexer.get_csrs() diff --git a/misoclib/mem/sdram/core/lasmicon/multiplexer.py b/misoclib/mem/sdram/core/lasmicon/multiplexer.py index c896480a9..cb1fe53f7 100644 --- a/misoclib/mem/sdram/core/lasmicon/multiplexer.py +++ b/misoclib/mem/sdram/core/lasmicon/multiplexer.py @@ -89,7 +89,8 @@ class _Steerer(Module): ] class Multiplexer(Module, AutoCSR): - def __init__(self, phy, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic): + def __init__(self, phy, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic, + with_bandwidth_measurement=False): assert(phy.settings.nphases == len(dfi.phases)) # Command choosing @@ -211,4 +212,5 @@ class Multiplexer(Module, AutoCSR): fsm.finalize() self.comb += refresher.ack.eq(fsm.state == fsm.encoding["REFRESH"]) - self.submodules.bandwidth = Bandwidth(choose_req.cmd) + if with_bandwidth_measurement: + self.submodules.bandwidth = Bandwidth(choose_req.cmd)