From 422b02cc16f1fa8d3002e0bef43120e69e216a47 Mon Sep 17 00:00:00 2001
From: Andrew Dennison <andrew@motec.com.au>
Date: Sun, 25 Feb 2024 11:13:45 +1100
Subject: [PATCH] cores/spi_mmap: fix data in unused rx_fifo bits

clear miso at start. Prevent previous transfer data in unused bits
with 8 and 16bit slot lengths and 32bit bus read. Fixes 2 tests.
---
 litex/soc/cores/spi/spi_mmap.py | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/litex/soc/cores/spi/spi_mmap.py b/litex/soc/cores/spi/spi_mmap.py
index 4932248a1..17b2ca8c0 100644
--- a/litex/soc/cores/spi/spi_mmap.py
+++ b/litex/soc/cores/spi/spi_mmap.py
@@ -206,7 +206,10 @@ class SPIMaster(LiteXModule):
         self.sync += [
             If(miso_shift,
                 miso_data.eq(Cat(miso, miso_data))
-            )
+            ),
+            If(self.start,
+                miso_data.eq(0)
+            ),
         ]
         self.comb += self.miso.eq(miso_data)