diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index b0906182f..78a0aa88b 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -27,7 +27,7 @@ _reserved_keywords = {
     "specify", "specparam", "strong0", "strong1", "supply0", "supply1",
     "table", "task", "time", "tran", "tranif0", "tranif1", "tri", "tri0",
     "tri1", "triand", "trior", "trireg", "unsigned", "use", "vectored", "wait",
-    "wand", "weak0", "weak1", "while", "wire", "wor","xnor", "xor"
+    "wand", "weak0", "weak1", "while", "wire", "wor","xnor", "xor", "do"
 }