From 4329e3e1b996671daecec7c7b9e0326c4de442a9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 12 Apr 2015 14:27:29 +0200 Subject: [PATCH] liteeth/phy/mii: allow use of MII phy on GMII/MII chips that do not have phy clock provided by the FPGA (tested on KC705) --- misoclib/com/liteeth/phy/mii.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/misoclib/com/liteeth/phy/mii.py b/misoclib/com/liteeth/phy/mii.py index 779c8e3d8..13d39ffb0 100644 --- a/misoclib/com/liteeth/phy/mii.py +++ b/misoclib/com/liteeth/phy/mii.py @@ -94,7 +94,8 @@ class LiteEthPHYMIICRG(Module, AutoCSR): def __init__(self, clock_pads, pads, with_hw_init_reset): self._reset = CSRStorage() ### - self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy) + if hasattr(clock_pads, "phy"): + self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy) self.clock_domains.cd_eth_rx = ClockDomain() self.clock_domains.cd_eth_tx = ClockDomain()