diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c
index 8c5959ce7..3a1497157 100644
--- a/litex/soc/software/bios/main.c
+++ b/litex/soc/software/bios/main.c
@@ -384,8 +384,10 @@ static void do_command(char *c)
 	else if(strcmp(token, "sdrrderr") == 0) sdrrderr(get_token(&c));
 	else if(strcmp(token, "sdrwr") == 0) sdrwr(get_token(&c));
 #ifdef CSR_DDRPHY_BASE
+#ifndef A7DDRPHY_BITSLIP
 	else if(strcmp(token, "sdrwlon") == 0) sdrwlon();
 	else if(strcmp(token, "sdrwloff") == 0) sdrwloff();
+#endif
 	else if(strcmp(token, "sdrlevel") == 0) sdrlevel();
 #endif
 	else if(strcmp(token, "memtest") == 0) memtest();
diff --git a/litex/soc/software/bios/sdram.c b/litex/soc/software/bios/sdram.c
index 3a8131400..8771f384e 100644
--- a/litex/soc/software/bios/sdram.c
+++ b/litex/soc/software/bios/sdram.c
@@ -195,6 +195,7 @@ void sdrwr(char *startaddr)
 }
 
 #ifdef CSR_DDRPHY_BASE
+#ifndef A7DDRPHY_BITSLIP
 
 void sdrwlon(void)
 {
@@ -214,7 +215,6 @@ void sdrwloff(void)
 
 #define ERR_DDRPHY_DELAY 32
 
-#ifndef SDRAM_ISERDESE2_BITSLIP
 static int write_level(int *delay, int *high_skew)
 {
 	int i;
@@ -284,11 +284,6 @@ static int write_level(int *delay, int *high_skew)
 
 	return ok;
 }
-#else
-static int write_level(int *delay, int *high_skew)
-{
-}
-#endif
 
 static void read_bitslip(int *delay, int *high_skew)
 {
@@ -415,7 +410,7 @@ static void read_delays(void)
 
 	printf("completed\n");
 }
-
+#endif /* A7DDRPHY_BITSLIP */
 #endif /* CSR_DDRPHY_BASE */
 
 static unsigned int seed_to_data_32(unsigned int seed, int random)
@@ -557,7 +552,27 @@ int memtest(void)
 }
 
 #ifdef CSR_DDRPHY_BASE
-int sdrlevel_generic(void)
+#ifdef A7DDRPHY_BITSLIP
+int sdrlevel(void)
+{
+	int bitslip, delay, module;
+	int i;
+	sdram_dfii_control_write(DFII_CONTROL_SEL);
+	for(module=0; module<8; module++) {
+		ddrphy_dly_sel_write(1<<module);
+		ddrphy_rdly_dq_rst_write(1);
+		for(bitslip=0; bitslip<A7DDRPHY_BITSLIP; bitslip++) {
+			// 7-series SERDES in DDR mode needs 3 pulses for 1 bitslip
+			for(i=0; i<3; i++)
+				ddrphy_rdly_dq_bitslip_write(1);
+		}
+		for(delay=0; delay<A7DDRPHY_DELAY; delay++)
+			ddrphy_rdly_dq_inc_write(1);
+	}
+	return 1;
+}
+#else
+int sdrlevel(void)
 {
 	int delay[DFII_PIX_DATA_SIZE/2];
 	int high_skew[DFII_PIX_DATA_SIZE/2];
@@ -569,38 +584,7 @@ int sdrlevel_generic(void)
 
 	return 1;
 }
-
-#ifdef SDRAM_ISERDESE2_BITSLIP
-static int sdrlevel_artix7(void)
-{
-	int bitslip, delay, module;
-	int i;
-	sdram_dfii_control_write(DFII_CONTROL_SEL);
-	for(module=0; module<8; module++) {
-		ddrphy_dly_sel_write(1<<module);
-		ddrphy_rdly_dq_rst_write(1);
-		for(bitslip=0; bitslip<SDRAM_ISERDESE2_BITSLIP; bitslip++) {
-			// 7-series SERDES in DDR mode needs 3 pulses for 1 bitslip
-			for(i=0; i<3; i++)
-				ddrphy_rdly_dq_bitslip_write(1);
-		}
-		for(delay=0; delay<SDRAM_IDELAYE2_DELAY; delay++)
-			ddrphy_rdly_dq_inc_write(1);
-	}
-	return 1;
-}
 #endif
-
-int sdrlevel(void)
-{
-#ifdef SDRAM_ISERDESE2_BITSLIP
-	if(!sdrlevel_artix7())
-		return 0;
-#else
-	if(!sdrlevel_generic())
-		return 0;
-#endif
-}
 #endif
 
 int sdrinit(void)