From 4524262f64e5c0d860a20eba419ecb94528b9880 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 26 Oct 2023 17:18:38 +0200 Subject: [PATCH] axi/axi_lite: Add addressing parameters and assert on byte. Useful to have similar properties than Wishbone. --- litex/soc/interconnect/axi/axi_lite.py | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/litex/soc/interconnect/axi/axi_lite.py b/litex/soc/interconnect/axi/axi_lite.py index 26bb1dd46..6c7ad3db9 100644 --- a/litex/soc/interconnect/axi/axi_lite.py +++ b/litex/soc/interconnect/axi/axi_lite.py @@ -44,13 +44,22 @@ def r_lite_description(data_width): ] class AXILiteInterface: - def __init__(self, data_width=32, address_width=32, clock_domain="sys", name=None, bursting=False): - self.data_width = data_width - self.address_width = address_width - self.clock_domain = clock_domain + def __init__(self, data_width=32, address_width=32, addressing="byte", clock_domain="sys", name=None, bursting=False): + # Parameters checks. + # ------------------ + assert addressing == "byte" if bursting is not False: raise NotImplementedError("AXI-Lite does not support bursting") + # Parameters. + # ----------- + self.data_width = data_width + self.address_width = address_width + self.addressing = addressing + self.clock_domain = clock_domain + + # Channels. + # --------- self.aw = stream.Endpoint(ax_lite_description(address_width), name=name) self.w = stream.Endpoint(w_lite_description(data_width), name=name) self.b = stream.Endpoint(b_lite_description(), name=name)