diff --git a/miscope/com/uart2vb/host/uart2wb.py b/miscope/com/uart2vb/host/uart2wb.py new file mode 100644 index 000000000..2d86cc004 --- /dev/null +++ b/miscope/com/uart2vb/host/uart2wb.py @@ -0,0 +1,89 @@ +import string +import time +import serial +from struct import * +import time + +WRITE_CMD = 0x01 +READ_CMD = 0x02 +CLOSE_CMD = 0x03 + +def write_b(uart, data): + uart.write(pack('B',data)) + +class Uart2Wb: + def __init__(self, port, baudrate, debug = False): + self.port = port + self.baudrate = baudrate + self.debug = debug + self.uart = serial.Serial(port, baudrate, timeout=0.25) + + def open(self): + self.uart.write("\nuart2wb\n".encode('ascii')) + self.uart.flush() + time.sleep(0.1) + self.uart.close() + self.uart.open() + + def close(self): + for i in range(16): + write_b(self.uart, CLOSE_CMD) + self.uart.close() + + def read(self, addr, burst_length=1): + write_b(self.uart, READ_CMD) + write_b(self.uart, burst_length) + write_b(self.uart, (addr & 0xff000000) >> 24) + write_b(self.uart, (addr & 0x00ff0000) >> 16) + write_b(self.uart, (addr & 0x0000ff00) >> 8) + write_b(self.uart, (addr & 0x000000ff)) + values = [] + for i in range(burst_length): + read = self.uart.read(4) + val = (int(read[0]) << 24) | (int(read[1]) << 16) | (int(read[2]) << 8) | int(read[3]) + if self.debug: + print("RD %08X @ %08X" %(val, addr + 4*i)) + values.append(val) + if burst_length == 1: + return values[0] + else: + return values + + def read_csr(self, addr, burst_length=1): + values = self.read(addr, burst_length) + if isinstance(values, list): + for i in range(len(values)): + values[i] = values[i]&0xff + else: + values = values & 0xff + return values + + def write(self, addr, data): + if isinstance(data, list): + burst_length = len(data) + else: + burst_length = 1 + write_b(self.uart, WRITE_CMD) + write_b(self.uart, burst_length) + self.uart.write([(addr & 0xff000000) >> 24, + (addr & 0x00ff0000) >> 16, + (addr & 0x0000ff00) >> 8, + (addr & 0x000000ff)]) + if isinstance(data, list): + for i in range(len(data)): + self.uart.write([(data[i] & 0xff000000) >> 24, + (data[i] & 0x00ff0000) >> 16, + (data[i] & 0x0000ff00) >> 8, + (data[i] & 0x000000ff)]) + if self.debug: + print("WR %08X @ %08X" %(elt, addr + 4*i)) + else: + self.uart.write([(data & 0xff000000) >> 24, + (data & 0x00ff0000) >> 16, + (data & 0x0000ff00) >> 8, + (data & 0x000000ff)]) + if self.debug: + print("WR %08X @ %08X" %(data, addr)) + + def write_csr(self, addr, data): + self.write(addr, data) \ No newline at end of file diff --git a/miscope/com/uart2vb/lm32/uart2wb.c b/miscope/com/uart2vb/lm32/uart2wb.c new file mode 100644 index 000000000..dcd9cada5 --- /dev/null +++ b/miscope/com/uart2vb/lm32/uart2wb.c @@ -0,0 +1,53 @@ +// Use this code in your LM32 code to control CSR +// over uart + +#define WRITE_CMD 0x01 +#define READ_CMD 0x02 +#define CLOSE_CMD 0x03 +#define MMPTR(x) (*((volatile unsigned int *)(x))) + +static void uart2wb(void) +{ + unsigned char cmd; + unsigned char burst_length; + unsigned char adr_t[4]; + unsigned int adr; + char data_t[4]; + unsigned int data; + unsigned char i; + unsigned char j; + + while(cmd != CLOSE_CMD) + { + cmd = readchar(); + + if (cmd == WRITE_CMD) + { + burst_length = readchar(); + for(i=0;i<4;i++) adr_t[i] = readchar(); + adr = adr_t[0]<<24 | adr_t[1]<<16 | adr_t[2]<<8 | adr_t[3]; + for(i=0;i>24; + data_t[1] = (data & 0x00ff0000)>>16; + data_t[2] = (data & 0x0000ff00)>>8; + data_t[3] = (data & 0x000000ff); + for(j=0;j<4;j++) putchar(data_t[j]); + } + } + } +}