From 458e0057f27231bfee482c76873421a74cbde9c3 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 9 Sep 2024 18:18:59 +0200
Subject: [PATCH] soc/interconnect/wishbone: Add Bypass mode on Cache when
 cachesize == 0 and similar data_widths.

---
 litex/soc/interconnect/wishbone.py | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index 0231190f0..37f190ce5 100644
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -659,6 +659,12 @@ class Cache(LiteXModule):
         if dw_to < dw_from and (dw_from % dw_to) != 0:
             raise ValueError("Master data width must be a multiple of {dw}".format(dw=dw_to))
 
+        # Bypass.
+        # -------
+        if (cachesize == 0) and (dw_to == dw_from):
+            self.comb += master.connect(slave)
+            return
+
         # Address Split.
         # --------------
         # TAG | LINE NUMBER | LINE OFFSET.