From 3b9e4c4df69b2178cdb3ce631cef8f990a1818ae Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 25 Nov 2018 12:56:37 -0800 Subject: [PATCH 1/2] wishbone.SRAM: Support non-32bit wishbone widths. --- litex/soc/interconnect/wishbone.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index 93a312668..7e8b78d7b 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -651,7 +651,7 @@ class SRAM(Module): # generate write enable signal if not read_only: self.comb += [port.we[i].eq(self.bus.cyc & self.bus.stb & self.bus.we & self.bus.sel[i]) - for i in range(4)] + for i in range(bus_data_width//8)] # address and data self.comb += [ port.adr.eq(self.bus.adr[:len(port.adr)]), From 4f565c51796aae7a63419c2f203b1d32dc20af74 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 25 Nov 2018 12:57:11 -0800 Subject: [PATCH 2/2] stream.Endpoint: Pass extra arguments to superclass. --- litex/soc/interconnect/stream.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py index 5a070ea7e..2974b7a0f 100644 --- a/litex/soc/interconnect/stream.py +++ b/litex/soc/interconnect/stream.py @@ -41,12 +41,12 @@ class EndpointDescription: class Endpoint(Record): - def __init__(self, description_or_layout): + def __init__(self, description_or_layout, name=None, **kwargs): if isinstance(description_or_layout, EndpointDescription): self.description = description_or_layout else: self.description = EndpointDescription(description_or_layout) - Record.__init__(self, self.description.get_full_layout()) + Record.__init__(self, self.description.get_full_layout(), name, **kwargs) def __getattr__(self, name): try: