From 45b0c8dcd34e5441e6d023ff31598899daa7d782 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 12 Oct 2023 12:29:25 +0200 Subject: [PATCH] core/naxriscv update --- litex/soc/cores/cpu/naxriscv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index 65aaf989d..439f21ec6 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -309,7 +309,7 @@ class NaxRiscv(CPU): if NaxRiscv.update_repo != "no": NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "coherency", "4da1cd82" if NaxRiscv.update_repo=="recommended" else None) - NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "bus-fabric" , "8eed9583" if NaxRiscv.update_repo=="recommended" else None) + NaxRiscv.git_setup("SpinalHDL", sdir, "https://github.com/SpinalHDL/SpinalHDL.git", "bus-fabric" , "74c5d7de" if NaxRiscv.update_repo=="recommended" else None) gen_args = [] gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}")