From 45eb5090dba31fabfce71e1051c8dc59817808f5 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 21 Mar 2015 18:41:59 +0100
Subject: [PATCH] sdram/module: add speedgrate note for IS42S16160 and
 AS4C16M16

---
 misoclib/mem/sdram/module.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/misoclib/mem/sdram/module.py b/misoclib/mem/sdram/module.py
index 109e51d06..e41bced06 100644
--- a/misoclib/mem/sdram/module.py
+++ b/misoclib/mem/sdram/module.py
@@ -49,6 +49,7 @@ class IS42S16160(SDRAMModule):
 		"nrows":	8192,
 		"ncols":	512
 	}
+	# Note: timings for -7 speedgrade (add support for others speedgrades)
 	timing_settings = {
 		"tRP":		20,
 		"tRCD":		20,
@@ -85,6 +86,7 @@ class AS4C16M16(SDRAMModule):
 		"nrows":	8192,
 		"ncols":	512
 	}
+	# Note: timings for -6 speedgrade (add support for others speedgrades)
 	timing_settings = {
 		"tRP":		18,
 		"tRCD":		18,