From 46107137975850b895e8d7cd56040898d1ec060b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 8 Nov 2023 16:57:21 +0100 Subject: [PATCH] gen/fhdl/verilog: Ensure top is not None to build hierarchy. --- litex/gen/fhdl/verilog.py | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py index 12d8953f8..d8b0dad61 100644 --- a/litex/gen/fhdl/verilog.py +++ b/litex/gen/fhdl/verilog.py @@ -90,13 +90,16 @@ def _generate_timescale(time_unit="1ns", time_precision="1ps"): # ------------------------------------------------------------------------------------------------ # def _generate_hierarchy(top): - hierarchy_explorer = LiteXHierarchyExplorer(top=top, depth=None, with_colors=False) - r = "/*\n" - for l in hierarchy_explorer.get_hierarchy().split("\n"): - r += l + "\n" - r = r[:-1] - r += "*/\n" - return r + if top is None: + return "" + else: + hierarchy_explorer = LiteXHierarchyExplorer(top=top, depth=None, with_colors=False) + r = "/*\n" + for l in hierarchy_explorer.get_hierarchy().split("\n"): + r += l + "\n" + r = r[:-1] + r += "*/\n" + return r # ------------------------------------------------------------------------------------------------ # # RESERVED KEYWORDS #