From 4627e8958f4164abc9c2dc4baab6e63eba1e2c76 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 3 Nov 2023 12:11:53 +0100
Subject: [PATCH] gen/fhdl/instance: Generate Parameters/Inputs/Outputs/InOuts
 separators and generate IOs in Input/Output/InOut order.

---
 litex/gen/fhdl/instance.py | 29 +++++++++++++++++++----------
 1 file changed, 19 insertions(+), 10 deletions(-)

diff --git a/litex/gen/fhdl/instance.py b/litex/gen/fhdl/instance.py
index 47f1913b1..1eac1f115 100644
--- a/litex/gen/fhdl/instance.py
+++ b/litex/gen/fhdl/instance.py
@@ -29,6 +29,7 @@ def _instance_generate_verilog(instance, ns, add_data_file):
     if parameters:
         r += "#(\n"
         first = True
+        r += "\t// Parameters.\n"
         for p in parameters:
             if not first:
                 r += ",\n"
@@ -56,16 +57,24 @@ def _instance_generate_verilog(instance, ns, add_data_file):
     r += ns.get_name(instance)
     if parameters:
         r += " "
-    r += "(\n"
+    r += "("
+    inputs  = list(filter(lambda i: isinstance(i, Instance.Input),  instance.items))
+    outputs = list(filter(lambda i: isinstance(i, Instance.Output), instance.items))
+    inouts  = list(filter(lambda i: isinstance(i, Instance.InOut),  instance.items))
     first = True
-    for io in instance.items:
-        if isinstance(io, Instance._IO):
-            name_inst   = io.name
-            name_design = verilog_printexpr(ns, io.expr)[0]
-            if not first:
-                r += ",\n"
-            first = False
-            r += "\t." + name_inst + "(" + name_design + ")"
+    for io in (inputs + outputs + inouts):
+        if not first:
+            r += ",\n"
+        if len(inputs) and (io is inputs[0]):
+            r += "\n\t// Inputs.\n"
+        if len(outputs) and (io is outputs[0]):
+            r += "\n\t// Outputs.\n"
+        if len(inouts) and (io is inouts[0]):
+            r += "\n\t// InOuts.\n"
+        name_inst   = io.name
+        name_design = verilog_printexpr(ns, io.expr)[0]
+        first = False
+        r += f"\t.{name_inst}({name_design})"
     if not first:
         r += "\n"
 
@@ -73,7 +82,7 @@ def _instance_generate_verilog(instance, ns, add_data_file):
     # -----------------------------
     if instance.synthesis_directive is not None:
         synthesis_directive = f"/* synthesis {instance.synthesis_directive} */"
-        r += ")" + synthesis_directive + ";\n"
+        r += f"){synthesis_directive};\n"
     else:
         r += ");\n"