From d8df6cb27d0d2611ab4e4fd41d303c111525581c Mon Sep 17 00:00:00 2001 From: Sylvain Munaut Date: Wed, 2 Mar 2022 14:12:18 +0100 Subject: [PATCH] cores/jtag/XilinxJTAG: Add support for Zynq UltraScale+ Signed-off-by: Sylvain Munaut --- litex/soc/cores/jtag.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/jtag.py b/litex/soc/cores/jtag.py index 88b9da75e..b7ce1f990 100644 --- a/litex/soc/cores/jtag.py +++ b/litex/soc/cores/jtag.py @@ -308,7 +308,7 @@ class XilinxJTAG(Module): prim_dict = { # Primitive Name Ðevice (startswith) "BSCAN_SPARTAN6" : ["xc6"], - "BSCANE2" : ["xc7", "xcku", "xcvu"], + "BSCANE2" : ["xc7", "xcku", "xcvu", "xczu"], } for prim, prim_devs in prim_dict.items(): for prim_dev in prim_devs: