diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py
old mode 100644
new mode 100755
index 63e63ec07..2d936ddf0
--- a/litex/soc/cores/cpu/naxriscv/core.py
+++ b/litex/soc/cores/cpu/naxriscv/core.py
@@ -396,7 +396,7 @@ class NaxRiscv(CPU):
         )
         soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False))
 
-    def add_memory_buses(self, address_width, data_width):
+    def add_memory_buses(self, address_width, data_width, accessible_region):
         nax_data_width = 64
         nax_burst_size = 64
         assert data_width >= nax_data_width   # FIXME: Only supporting up-conversion for now.
@@ -460,6 +460,10 @@ class NaxRiscv(CPU):
             i_ram_dbus_rresp   = dbus.r.resp,
             i_ram_dbus_rlast   = dbus.r.last,
         )
+        self.scala_args.append('mem-region-origin=0x{accessible_region.origin:x}'
+                               .format(accessible_region=accessible_region))
+        self.scala_args.append('mem-region-length=0x{accessible_region.size:x}'
+                               .format(accessible_region=accessible_region))
 
     def do_finalize(self):
         assert hasattr(self, "reset_address")
diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py
index e6728711c..40f7d8d35 100755
--- a/litex/soc/cores/cpu/vexriscv_smp/core.py
+++ b/litex/soc/cores/cpu/vexriscv_smp/core.py
@@ -430,7 +430,7 @@ class VexRiscvSMP(CPU):
         )
         soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x1_0000, cached=False))
 
-    def add_memory_buses(self, address_width, data_width):
+    def add_memory_buses(self, address_width, data_width, accessible_region):
         VexRiscvSMP.litedram_width = data_width
 
         from litedram.common import LiteDRAMNativePort
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
old mode 100644
new mode 100755
index d20e33680..6f6149693
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1460,13 +1460,16 @@ class LiteXSoC(SoC):
             sdram_size = min(sdram_size, size)
 
         # Add SDRAM region.
-        self.bus.add_region("main_ram", SoCRegion(origin=self.mem_map.get("main_ram", origin), size=sdram_size))
+        main_ram_region = SoCRegion(origin=self.mem_map.get("main_ram", origin), 
+                                    size=sdram_size)
+        self.bus.add_region("main_ram", main_ram_region)
 
         # Add CPU's direct memory buses (if not already declared) ----------------------------------
         if hasattr(self.cpu, "add_memory_buses"):
             self.cpu.add_memory_buses(
-                address_width = 32,
-                data_width    = sdram.crossbar.controller.data_width
+                address_width     = 32,
+                data_width        = sdram.crossbar.controller.data_width,
+                accessible_region = main_ram_region
             )
 
         # Connect CPU's direct memory buses to LiteDRAM --------------------------------------------