From 47291e07f780e2217ee8a7b711e801b3496be661 Mon Sep 17 00:00:00 2001 From: Michal Sieron Date: Thu, 26 Aug 2021 18:07:03 +0200 Subject: [PATCH] Set TX UART pin high on reset Without this we get corrupted data on the output after SoC reset. It was present there, but got removed in 908e72e65ba42114ac398a0a0710a08d9c6d03d0 refactor. Fixes #991 --- litex/soc/cores/uart.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index eff637cad..650674271 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -57,6 +57,8 @@ class RS232PHYTX(Module): # # # + pads.tx.reset = 1 + data = Signal(8, reset_less=True) count = Signal(4, reset_less=True)