From 8bb10e161789eabb2552a4571071305777306cc2 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 12 Jun 2024 11:25:18 +0200 Subject: [PATCH 1/5] cpu/vexii: Add AXI3 support via --with-axi3 --- litex/soc/cores/cpu/vexiiriscv/core.py | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index 93b941ce6..4ebf865ce 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -56,6 +56,7 @@ class VexiiRiscv(CPU): with_rvd = False with_rva = False with_dma = False + with_axi3 = False jtag_tap = False jtag_instruction = False vexii_args = "" @@ -135,6 +136,7 @@ class VexiiRiscv(CPU): cpu_group.add_argument("--l2-bytes", default=0, help="VexiiRiscv L2 bytes, default 128 KB.") cpu_group.add_argument("--l2-ways", default=0, help="VexiiRiscv L2 ways, default 8.") cpu_group.add_argument("--l2-self-flush", default=None, help="VexiiRiscv L2 ways will self flush on from,to,cycles") + cpu_group.add_argument("--with-axi3", action="store_true", help="mbus will be axi3 instead of axi4") @@ -146,7 +148,7 @@ class VexiiRiscv(CPU): vdir = get_data_mod("cpu", "vexiiriscv").data_location ndir = os.path.join(vdir, "ext", "VexiiRiscv") - NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "32ec8bd1", args.update_repo) + NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "66974d1e", args.update_repo) if not args.cpu_variant: args.cpu_variant = "standard" @@ -172,6 +174,7 @@ class VexiiRiscv(CPU): VexiiRiscv.jtag_tap = args.with_jtag_tap VexiiRiscv.jtag_instruction = args.with_jtag_instruction VexiiRiscv.with_dma = args.with_coherent_dma + VexiiRiscv.with_axi3 = args.with_axi3 VexiiRiscv.update_repo = args.update_repo VexiiRiscv.no_netlist_cache = args.no_netlist_cache VexiiRiscv.vexii_args += " " + args.vexii_args @@ -321,6 +324,7 @@ class VexiiRiscv(CPU): md5_hash.update(str(VexiiRiscv.jtag_tap).encode('utf-8')) md5_hash.update(str(VexiiRiscv.jtag_instruction).encode('utf-8')) md5_hash.update(str(VexiiRiscv.with_dma).encode('utf-8')) + md5_hash.update(str(VexiiRiscv.with_axi3).encode('utf-8')) md5_hash.update(str(VexiiRiscv.memory_regions).encode('utf-8')) md5_hash.update(str(VexiiRiscv.vexii_args).encode('utf-8')) # md5_hash.update(str(VexiiRiscv.internal_bus_width).encode('utf-8')) @@ -355,6 +359,8 @@ class VexiiRiscv(CPU): gen_args.append(f"--with-jtag-instruction") if(VexiiRiscv.with_dma) : gen_args.append(f"--with-dma") + if(VexiiRiscv.with_axi3) : + gen_args.append(f"--with-axi3") cmd = f"""cd {ndir} && sbt "runMain vexiiriscv.soc.litex.SocGen {" ".join(gen_args)}\"""" print("VexiiRiscv generation command :") @@ -471,7 +477,8 @@ class VexiiRiscv(CPU): mbus = axi.AXIInterface( data_width = VexiiRiscv.litedram_width, address_width = 32, - id_width = 8, #TODO + id_width = 8, + version = "axi3" if VexiiRiscv.with_axi3 else "axi4" ) self.memory_buses.append(mbus) From 2e4813d6ae1a1899689e3a07eff61a5192a239b4 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 12 Jun 2024 19:33:20 +0200 Subject: [PATCH 2/5] Fix vexii axi3 --- litex/soc/cores/cpu/vexiiriscv/core.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index 4ebf865ce..1a1b37cc1 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -534,6 +534,11 @@ class VexiiRiscv(CPU): i_mBus_rlast = mbus.r.last, ) + if VexiiRiscv.with_axi3: + self.cpu_params.update( + o_mBus_wid=mbus.w.id + ) + def do_finalize(self): assert hasattr(self, "reset_address") From 28d4aff10f09b0835297f4bf3d26364dcc8850f3 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 13 Jun 2024 23:20:25 +0200 Subject: [PATCH 3/5] vexii non coherent config write bandwidth improvment --- litex/soc/cores/cpu/vexiiriscv/core.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index 1a1b37cc1..297e8362b 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -148,7 +148,7 @@ class VexiiRiscv(CPU): vdir = get_data_mod("cpu", "vexiiriscv").data_location ndir = os.path.join(vdir, "ext", "VexiiRiscv") - NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "66974d1e", args.update_repo) + NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "e991b315", args.update_repo) if not args.cpu_variant: args.cpu_variant = "standard" From 1267ba8ae6f2676d2460e1ae4f8953293315ce32 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 10 Jul 2024 09:35:34 +0200 Subject: [PATCH 4/5] Update Nax/Vexii --- litex/soc/cores/cpu/naxriscv/core.py | 5 ++++- litex/soc/cores/cpu/vexiiriscv/core.py | 4 +++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index 090ffceca..004bde94a 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -322,7 +322,7 @@ class NaxRiscv(CPU): ndir = os.path.join(vdir, "ext", "NaxRiscv") sdir = os.path.join(vdir, "ext", "SpinalHDL") - NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "main", "f3357383", NaxRiscv.update_repo) + NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "main", "43195dd1", NaxRiscv.update_repo) gen_args = [] gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}") @@ -368,6 +368,7 @@ class NaxRiscv(CPU): # Add RAM. # By default, use Generic RAM implementation. ram_filename = "Ram_1w_1rs_Generic.v" + lutram_filename = "Ram_1w_1ra_Generic.v" # On Altera/Intel platforms, use specific implementation. from litex.build.altera import AlteraPlatform if isinstance(platform, AlteraPlatform): @@ -377,6 +378,8 @@ class NaxRiscv(CPU): if isinstance(platform, EfinixPlatform): ram_filename = "Ram_1w_1rs_Efinix.v" platform.add_source(os.path.join(vdir, ram_filename), "verilog") + platform.add_source(os.path.join(vdir, lutram_filename), "verilog") + # Add Cluster. platform.add_source(os.path.join(vdir, self.netlist_name + ".v"), "verilog") diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index 297e8362b..24a9618b5 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -148,7 +148,7 @@ class VexiiRiscv(CPU): vdir = get_data_mod("cpu", "vexiiriscv").data_location ndir = os.path.join(vdir, "ext", "VexiiRiscv") - NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "e991b315", args.update_repo) + NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "ee92608a", args.update_repo) if not args.cpu_variant: args.cpu_variant = "standard" @@ -378,6 +378,7 @@ class VexiiRiscv(CPU): # Add RAM. # By default, use Generic RAM implementation. ram_filename = "Ram_1w_1rs_Generic.v" + lutram_filename = "Ram_1w_1ra_Generic.v" # On Altera/Intel platforms, use specific implementation. from litex.build.altera import AlteraPlatform if isinstance(platform, AlteraPlatform): @@ -387,6 +388,7 @@ class VexiiRiscv(CPU): if isinstance(platform, EfinixPlatform): ram_filename = "Ram_1w_1rs_Efinix.v" platform.add_source(os.path.join(vdir, ram_filename), "verilog") + platform.add_source(os.path.join(vdir, lutram_filename), "verilog") # Add Cluster. platform.add_source(os.path.join(vdir, self.netlist_name + ".v"), "verilog") From 9fa1b4c123ab4d761e576ad3ec51c8b6658f5925 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 12 Jul 2024 16:17:30 +0200 Subject: [PATCH 5/5] Update Nax/Vexii --- litex/soc/cores/cpu/naxriscv/core.py | 3 +-- litex/soc/cores/cpu/vexiiriscv/core.py | 4 ++-- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index 0315cb827..e362fbf0a 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -320,9 +320,8 @@ class NaxRiscv(CPU): def generate_netlist(reset_address): vdir = get_data_mod("cpu", "naxriscv").data_location ndir = os.path.join(vdir, "ext", "NaxRiscv") - sdir = os.path.join(vdir, "ext", "SpinalHDL") - NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "main", "43195dd1", NaxRiscv.update_repo) + NaxRiscv.git_setup("NaxRiscv", ndir, "https://github.com/SpinalHDL/NaxRiscv.git", "main", "ba63ee6d", NaxRiscv.update_repo) gen_args = [] gen_args.append(f"--netlist-name={NaxRiscv.netlist_name}") diff --git a/litex/soc/cores/cpu/vexiiriscv/core.py b/litex/soc/cores/cpu/vexiiriscv/core.py index d63c83637..c15c2dc83 100755 --- a/litex/soc/cores/cpu/vexiiriscv/core.py +++ b/litex/soc/cores/cpu/vexiiriscv/core.py @@ -156,7 +156,7 @@ class VexiiRiscv(CPU): VexiiRiscv.vexii_args += " --with-mul --with-div --allow-bypass-from=0 --performance-counters=0" VexiiRiscv.vexii_args += " --fetch-l1 --fetch-l1-ways=2" VexiiRiscv.vexii_args += " --lsu-l1 --lsu-l1-ways=2 --with-lsu-bypass" - VexiiRiscv.vexii_args += " --relaxed-branch --relaxed-btb" + VexiiRiscv.vexii_args += " --relaxed-branch" if args.cpu_variant in ["linux", "debian"]: VexiiRiscv.vexii_args += " --with-rva --with-supervisor" @@ -164,7 +164,7 @@ class VexiiRiscv(CPU): VexiiRiscv.vexii_args += " --lsu-l1-ways=4 --lsu-l1-mem-data-width-min=64" if args.cpu_variant in ["debian"]: - VexiiRiscv.vexii_args += " --xlen=64 --with-rvc --with-rvf --with-rvd --fma-reduced-accuracy" + VexiiRiscv.vexii_args += " --xlen=64 --with-rvc --with-rvf --with-rvd --fma-reduced-accuracy --fpu-ignore-subnormal" if args.cpu_variant in ["linux", "debian"]: VexiiRiscv.vexii_args += " --with-btb --with-ras --with-gshare"