From 48ab96fd43dba9cdc850b66378f99deed8a24fee Mon Sep 17 00:00:00 2001
From: Andrew Dennison <andrew@motec.com.au>
Date: Sat, 2 Sep 2023 11:40:58 +1000
Subject: [PATCH] soc/intregation: fix cpu name in logging

Fixed CPU name being reported as irq name in logging.

```
INFO:SoC:CPU vexriscv_smp adding Interrupt(s).
INFO:SoCIRQHandler:noirq IRQ added at Location 0.
INFO:SoC:CPU noirq adding DMA Bus.
INFO:SoCDMABusHandler:Creating Bus Handler...
```
---
 litex/soc/integration/soc.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 72ae9acb4..2ed96f46b 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1113,8 +1113,8 @@ class SoC(LiteXModule, SoCCoreCompat):
                 self.irq.enable()
                 if hasattr(self.cpu, "reserved_interrupts"):
                     self.cpu.interrupts.update(self.cpu.reserved_interrupts)
-                for name, loc in self.cpu.interrupts.items():
-                    self.irq.add(name, loc)
+                for irq_name, loc in self.cpu.interrupts.items():
+                    self.irq.add(irq_name, loc)
                 self.add_config("CPU_HAS_INTERRUPT")
 
             # Create optional DMA Bus (for Cache Coherence).