From 48dc57470350be4fa3423bf762de2cd103833ee5 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 10 Dec 2020 14:33:29 +0100
Subject: [PATCH] integration/soc/add_uart: pass fifo_depth to UARTCrossover.

---
 litex/soc/integration/soc.py | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index ed5867cbe..92744b9f2 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1096,7 +1096,9 @@ class LiteXSoC(SoC):
 
         # Crossover
         elif name in ["crossover"]:
-            self.submodules.uart = uart.UARTCrossover()
+            self.submodules.uart = uart.UARTCrossover(
+                tx_fifo_depth = fifo_depth,
+                rx_fifo_depth = fifo_depth)
 
         # Model/Sim
         elif name in ["model", "sim"]: