From 48e5a1d14008cb8b33107ce20e9c642be815082a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 29 Sep 2019 17:04:21 +0200 Subject: [PATCH] soc/cores: uniformize (continue) --- litex/soc/cores/identifier.py | 1 + litex/soc/cores/prbs.py | 4 ++++ litex/soc/cores/timer.py | 4 +++- litex/soc/cores/uart.py | 1 + litex/soc/cores/usb_fifo.py | 4 ++++ litex/soc/cores/xadc.py | 22 ++++++++++++---------- 6 files changed, 25 insertions(+), 11 deletions(-) diff --git a/litex/soc/cores/identifier.py b/litex/soc/cores/identifier.py index 7dee940b2..fc0bf30a3 100644 --- a/litex/soc/cores/identifier.py +++ b/litex/soc/cores/identifier.py @@ -3,6 +3,7 @@ from migen import * +# Identifier --------------------------------------------------------------------------------------- class Identifier(Module): def __init__(self, ident): diff --git a/litex/soc/cores/prbs.py b/litex/soc/cores/prbs.py index 97ef4de6f..0b0ae7e25 100644 --- a/litex/soc/cores/prbs.py +++ b/litex/soc/cores/prbs.py @@ -8,6 +8,7 @@ from functools import reduce from migen import * from migen.genlib.cdc import MultiReg +# PRBS Generators ---------------------------------------------------------------------------------- class PRBSGenerator(Module): def __init__(self, n_out, n_state=23, taps=[17, 22]): @@ -43,6 +44,7 @@ class PRBS31Generator(PRBSGenerator): def __init__(self, n_out): PRBSGenerator.__init__(self, n_out, n_state=31, taps=[27, 30]) +# PRBS TX ------------------------------------------------------------------------------------------ class PRBSTX(Module): def __init__(self, width, reverse=False): @@ -86,6 +88,7 @@ class PRBSTX(Module): self.o.eq(prbs_data) ) +# PRBS Checkers ------------------------------------------------------------------------------------ class PRBSChecker(Module): def __init__(self, n_in, n_state=23, taps=[17, 22]): @@ -119,6 +122,7 @@ class PRBS31Checker(PRBSChecker): def __init__(self, n_out): PRBSChecker.__init__(self, n_out, n_state=31, taps=[27, 30]) +# PRBS RX ------------------------------------------------------------------------------------------ class PRBSRX(Module): def __init__(self, width, reverse=False): diff --git a/litex/soc/cores/timer.py b/litex/soc/cores/timer.py index def26cecd..3de9572ef 100644 --- a/litex/soc/cores/timer.py +++ b/litex/soc/cores/timer.py @@ -10,6 +10,8 @@ from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr_eventmanager import * from litex.soc.integration.doc import ModuleDoc +# Timer -------------------------------------------------------------------------------------------- + class Timer(Module, AutoCSR, ModuleDoc): """Timer @@ -56,7 +58,7 @@ class Timer(Module, AutoCSR, ModuleDoc): self._value = CSRStatus(width, description="""Latched countdown value""") self.submodules.ev = EventManager() - self.ev.zero = EventSourceProcess() + self.ev.zero = EventSourceProcess() self.ev.finalize() # # # diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py index 9a2d18676..2bdc8e30e 100644 --- a/litex/soc/cores/uart.py +++ b/litex/soc/cores/uart.py @@ -248,6 +248,7 @@ class UARTWishboneBridge(WishboneStreamingBridge): self.submodules.phy = RS232PHY(pads, clk_freq, baudrate) WishboneStreamingBridge.__init__(self, self.phy, clk_freq) +# UART Mutltiplexer -------------------------------------------------------------------------------- def UARTPads(): return Record([("tx", 1), ("rx", 1)]) diff --git a/litex/soc/cores/usb_fifo.py b/litex/soc/cores/usb_fifo.py index d818870a6..2388c2251 100644 --- a/litex/soc/cores/usb_fifo.py +++ b/litex/soc/cores/usb_fifo.py @@ -9,6 +9,7 @@ from migen.genlib.cdc import MultiReg from litex.soc.interconnect import stream +# Layout/Helpers ----------------------------------------------------------------------------------- def phy_description(dw): payload_layout = [("data", dw)] @@ -31,6 +32,7 @@ def anti_starvation(module, timeout): module.comb += max_time.eq(0) return en, max_time +# FT245 Synchronous FIFO Mode ---------------------------------------------------------------------- class FT245PHYSynchronous(Module): def __init__(self, pads, clk_freq, @@ -141,6 +143,7 @@ class FT245PHYSynchronous(Module): ) ] +# FT245 Asynchronous FIFO Mode --------------------------------------------------------------------- class FT245PHYAsynchronous(Module): def __init__(self, pads, clk_freq, @@ -329,6 +332,7 @@ class FT245PHYAsynchronous(Module): t += clk_period_ns/2 return math.ceil(t/clk_period_ns) +# FT245 FIFO Mode PHY (Automatic Asynchronous/Synchronous selection) ------------------------------- def FT245PHY(pads, *args, **kwargs): # autodetect PHY diff --git a/litex/soc/cores/xadc.py b/litex/soc/cores/xadc.py index 1b044d6f3..0cea38bb7 100644 --- a/litex/soc/cores/xadc.py +++ b/litex/soc/cores/xadc.py @@ -1,9 +1,11 @@ # Copyright 2014-2015 Robert Jordens +# License: BSD from migen import * from litex.soc.interconnect.csr import * +# XADC --------------------------------------------------------------------------------------------- class XADC(Module, AutoCSR): def __init__(self): @@ -17,16 +19,16 @@ class XADC(Module, AutoCSR): # Alarms self.alarm = Signal(8) - self.ot = Signal() + self.ot = Signal() # # # - busy = Signal() + busy = Signal() channel = Signal(7) - eoc = Signal() - eos = Signal() - data = Signal(16) - drdy = Signal() + eoc = Signal() + eos = Signal() + data = Signal(16) + drdy = Signal() self.specials += Instance("XADC", # from ug480 @@ -50,10 +52,10 @@ class XADC(Module, AutoCSR): ) channels = { - 0: self.temperature, - 1: self.vccint, - 2: self.vccaux, - 6: self.vccbram + 0: self.temperature, + 1: self.vccint, + 2: self.vccaux, + 6: self.vccbram } self.sync += [