From ea8ffd8e80744f829e2a9915ab707a96659361b4 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 14 Jul 2015 19:42:44 +0200 Subject: [PATCH 1/5] platforms/kc705: style --- mibuild/platforms/kc705.py | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py index 7b81945d1..a60b05b44 100644 --- a/mibuild/platforms/kc705.py +++ b/mibuild/platforms/kc705.py @@ -186,8 +186,7 @@ _io = [ ] _connectors = [ - ("HPC", - { + ("HPC", { "DP1_M2C_P": "D6", "DP1_M2C_N": "D5", "DP2_M2C_P": "B6", @@ -332,8 +331,7 @@ _connectors = [ "HA23_N": "L13", } ), - ("LPC", - { + ("LPC", { "GBTCLK0_M2C_P": "N8", "GBTCLK0_M2C_N": "N7", "LA01_CC_P": "AE23", From e56d80c7a008edb1b34f1202f5d9b79baab2a70b Mon Sep 17 00:00:00 2001 From: numato Date: Tue, 14 Jul 2015 11:15:00 -0600 Subject: [PATCH 2/5] Adding support for Numato Lab Mimas V2 platform --- mibuild/platforms/mimasv2.py | 245 +++++++++++++++++++++++++++++++++++ 1 file changed, 245 insertions(+) create mode 100644 mibuild/platforms/mimasv2.py diff --git a/mibuild/platforms/mimasv2.py b/mibuild/platforms/mimasv2.py new file mode 100644 index 000000000..aaa8aede5 --- /dev/null +++ b/mibuild/platforms/mimasv2.py @@ -0,0 +1,245 @@ +from mibuild.generic_platform import * +from mibuild.xilinx import XilinxPlatform + +_io = [ + ("clk100", 0, Pins("V10"), IOStandard("LVCMOS33")), + ("clk12", 0, Pins("D9"), IOStandard("LVCMOS33")), + + ( + "serial", + 0, + Subsignal("tx", Pins("A8"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), + Subsignal("rx", Pins("B8"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")) + ), + + ( + "spiflash", + 0, + Subsignal("cs_n", Pins("V3")), + Subsignal("clk", Pins("R15")), + Subsignal("mosi", Pins("T13")), + Subsignal("miso", Pins("R13"), Misc("PULLUP")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ), + + ( + "lpddr_clock", + 0, + Subsignal("p", Pins("G3")), + Subsignal("n", Pins("G1")), + IOStandard("MOBILE_DDR") + ), + + ( + "lpddr", + 0, + Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")), + Subsignal("ba", Pins("F2 F1")), + Subsignal("cke", Pins("H7")), + Subsignal("ras_n", Pins("L5")), + Subsignal("cas_n", Pins("K5")), + Subsignal("we_n", Pins("E3")), + Subsignal( + "dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 M3 M1 N2 N1 T2 T1 U2 U1") + ), + Subsignal("dqs", Pins("L4 P2")), + Subsignal("dm", Pins("K3 K4")), + IOStandard("MOBILE_DDR") + ), + + ("dipswitch", 0, Pins("C17"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("dipswitch", 1, Pins("C18"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("dipswitch", 2, Pins("D17"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("dipswitch", 3, Pins("D18"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("dipswitch", 4, Pins("E18"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("dipswitch", 5, Pins("E16"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("dipswitch", 6, Pins("F18"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("dipswitch", 7, Pins("F17"), IOStandard("LVCMOS33"), Misc("PULLUP")), + + ("buttonswitch", 0, Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("buttonswitch", 1, Pins("K17"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("buttonswitch", 2, Pins("L17"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("buttonswitch", 3, Pins("M16"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("buttonswitch", 4, Pins("L18"), IOStandard("LVCMOS33"), Misc("PULLUP")), + ("buttonswitch", 5, Pins("M18"), IOStandard("LVCMOS33"), Misc("PULLUP")), + + ("user_led", 0, Pins("T18"), IOStandard("LVCMOS33"), Drive(8)), + ("user_led", 1, Pins("T17"), IOStandard("LVCMOS33"), Drive(8)), + ("user_led", 2, Pins("U18"), IOStandard("LVCMOS33"), Drive(8)), + ("user_led", 3, Pins("U17"), IOStandard("LVCMOS33"), Drive(8)), + ("user_led", 4, Pins("N16"), IOStandard("LVCMOS33"), Drive(8)), + ("user_led", 5, Pins("N15"), IOStandard("LVCMOS33"), Drive(8)), + ("user_led", 6, Pins("P16"), IOStandard("LVCMOS33"), Drive(8)), + ("user_led", 7, Pins("P15"), IOStandard("LVCMOS33"), Drive(8)), + + ( + "microsd", + 0, + Subsignal( + "dat0", + Pins("K14"), + IOStandard("LVCMOS33"), + Misc("SLEW=FAST") + ), + + Subsignal( + "dat1", + Pins("G18"), + IOStandard("LVCMOS33"), + Misc("SLEW=FAST") + ), + + Subsignal( + "dat2", + Pins("J13"), + IOStandard("LVCMOS33"), + Misc("SLEW=FAST") + ), + + Subsignal( + "dat3", + Pins("L13"), + IOStandard("LVCMOS33"), + Misc("SLEW=FAST") + ), + + Subsignal( + "cmd", + Pins("G16"), + IOStandard("LVCMOS33"), + Misc("SLEW=FAST") + ), + + Subsignal( + "clk", + Pins("L12"), + IOStandard("LVCMOS33"), + Misc("SLEW=FAST") + ) + ), + + ( + "sevenseg", + 0, + Subsignal("segment7", Pins("A3"), IOStandard("LVCMOS33")), # A + Subsignal("segment6", Pins("B4"), IOStandard("LVCMOS33")), # B + Subsignal("segment5", Pins("A4"), IOStandard("LVCMOS33")), # C + Subsignal("segment4", Pins("C4"), IOStandard("LVCMOS33")), # D + Subsignal("segment3", Pins("C5"), IOStandard("LVCMOS33")), # E + Subsignal("segment2", Pins("D6"), IOStandard("LVCMOS33")), # F + Subsignal("segment1", Pins("C6"), IOStandard("LVCMOS33")), # G + Subsignal("segment0", Pins("A5"), IOStandard("LVCMOS33")), # Dot + Subsignal("enable0", Pins("B2"), IOStandard("LVCMOS33")), # EN0 + Subsignal("enable1", Pins("A2"), IOStandard("LVCMOS33")), # EN1 + Subsignal("enable2", Pins("B3"), IOStandard("LVCMOS33")) # EN2 + ), + + ( + "audio", + 0, + Subsignal( + "channel1", + Pins("B16"), + IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST") + ), + + Subsignal( + "channel2", + Pins("A16"), + IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST") + ) + ), + + ( + "vga", + 0, + Subsignal( + "hsync", + Pins("B12"), + IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST") + ), + + Subsignal( + "vsync", + Pins("A12"), + IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST") + ), + + Subsignal( + "red2", + Pins("C9"), + IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST") + ), + + Subsignal( + "red1", + Pins("B9"), + IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST") + ), + + Subsignal( + "red0", + Pins("A9"), + IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST") + ), + + Subsignal( + "green2", + Pins("C11"), + IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST") + ), + + Subsignal( + "green1", + Pins("A10"), + IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST") + ), + + Subsignal( + "green0", + Pins("C10"), + IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST") + ), + + Subsignal( + "blue2", + Pins("A11"), + IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST") + ), + + Subsignal( + "blue1", + Pins("B11"), + IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST") + ) + ) +] + +_connectors = [ + ("P6", "T3 R3 V5 U5 V4 T4 V7 U7"), + ("P7", "V11 U11 V13 U13 T10 R10 T11 R11"), + ("P8", "L16 L15 K16 K15 J18 J16 H18 H17") +] + + +class Platform(XilinxPlatform): + default_clk_name = "clk100" + default_clk_period = 10 + + def __init__(self): + XilinxPlatform.__init__(self, "xc6slx9-csg324-2", _io, _connectors) + + def create_programmer(self): + raise NotImplementedError From 52bdc2952865c6a9ade4c63ee43f983bd4c4b910 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 14 Jul 2015 19:56:00 +0200 Subject: [PATCH 3/5] mimasv2: style, consistency with other boards --- mibuild/platforms/mimasv2.py | 199 +++++++---------------------------- 1 file changed, 39 insertions(+), 160 deletions(-) diff --git a/mibuild/platforms/mimasv2.py b/mibuild/platforms/mimasv2.py index aaa8aede5..e31950b7b 100644 --- a/mibuild/platforms/mimasv2.py +++ b/mibuild/platforms/mimasv2.py @@ -1,38 +1,30 @@ from mibuild.generic_platform import * from mibuild.xilinx import XilinxPlatform + _io = [ ("clk100", 0, Pins("V10"), IOStandard("LVCMOS33")), ("clk12", 0, Pins("D9"), IOStandard("LVCMOS33")), - ( - "serial", - 0, - Subsignal("tx", Pins("A8"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")), - Subsignal("rx", Pins("B8"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")) - ), + ("serial", 0, + Subsignal("tx", Pins("A8"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST")), + Subsignal("rx", Pins("B8"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST"))), - ( - "spiflash", - 0, + ("spiflash", 0, Subsignal("cs_n", Pins("V3")), Subsignal("clk", Pins("R15")), Subsignal("mosi", Pins("T13")), Subsignal("miso", Pins("R13"), Misc("PULLUP")), - IOStandard("LVCMOS33"), Misc("SLEW=FAST") - ), + IOStandard("LVCMOS33"), Misc("SLEW=FAST")), - ( - "lpddr_clock", - 0, + ("ddram_clock", 0, Subsignal("p", Pins("G3")), Subsignal("n", Pins("G1")), - IOStandard("MOBILE_DDR") - ), + IOStandard("MOBILE_DDR")), - ( - "lpddr", - 0, + ("ddram", 0, Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")), Subsignal("ba", Pins("F2 F1")), Subsignal("cke", Pins("H7")), @@ -44,8 +36,7 @@ _io = [ ), Subsignal("dqs", Pins("L4 P2")), Subsignal("dm", Pins("K3 K4")), - IOStandard("MOBILE_DDR") - ), + IOStandard("MOBILE_DDR")), ("dipswitch", 0, Pins("C17"), IOStandard("LVCMOS33"), Misc("PULLUP")), ("dipswitch", 1, Pins("C18"), IOStandard("LVCMOS33"), Misc("PULLUP")), @@ -72,55 +63,17 @@ _io = [ ("user_led", 6, Pins("P16"), IOStandard("LVCMOS33"), Drive(8)), ("user_led", 7, Pins("P15"), IOStandard("LVCMOS33"), Drive(8)), - ( - "microsd", - 0, - Subsignal( - "dat0", - Pins("K14"), - IOStandard("LVCMOS33"), - Misc("SLEW=FAST") - ), + ("mmc", 0, + Subsignal("dat", Pins("K14 G18 J13 L13"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST")), - Subsignal( - "dat1", - Pins("G18"), - IOStandard("LVCMOS33"), - Misc("SLEW=FAST") - ), + Subsignal("cmd", Pins("G16"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST")), - Subsignal( - "dat2", - Pins("J13"), - IOStandard("LVCMOS33"), - Misc("SLEW=FAST") - ), + Subsignal("clk", Pins("L12"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST"))), - Subsignal( - "dat3", - Pins("L13"), - IOStandard("LVCMOS33"), - Misc("SLEW=FAST") - ), - - Subsignal( - "cmd", - Pins("G16"), - IOStandard("LVCMOS33"), - Misc("SLEW=FAST") - ), - - Subsignal( - "clk", - Pins("L12"), - IOStandard("LVCMOS33"), - Misc("SLEW=FAST") - ) - ), - - ( - "sevenseg", - 0, + ("sevenseg", 0, Subsignal("segment7", Pins("A3"), IOStandard("LVCMOS33")), # A Subsignal("segment6", Pins("B4"), IOStandard("LVCMOS33")), # B Subsignal("segment5", Pins("A4"), IOStandard("LVCMOS33")), # C @@ -129,102 +82,28 @@ _io = [ Subsignal("segment2", Pins("D6"), IOStandard("LVCMOS33")), # F Subsignal("segment1", Pins("C6"), IOStandard("LVCMOS33")), # G Subsignal("segment0", Pins("A5"), IOStandard("LVCMOS33")), # Dot - Subsignal("enable0", Pins("B2"), IOStandard("LVCMOS33")), # EN0 - Subsignal("enable1", Pins("A2"), IOStandard("LVCMOS33")), # EN1 - Subsignal("enable2", Pins("B3"), IOStandard("LVCMOS33")) # EN2 - ), + Subsignal("enable0", Pins("B2"), IOStandard("LVCMOS33")), # EN0 + Subsignal("enable1", Pins("A2"), IOStandard("LVCMOS33")), # EN1 + Subsignal("enable2", Pins("B3"), IOStandard("LVCMOS33"))), # EN2 - ( - "audio", - 0, - Subsignal( - "channel1", - Pins("B16"), - IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST") - ), - Subsignal( - "channel2", - Pins("A16"), - IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST") - ) - ), + ("audio", 0, + Subsignal("channel1", Pins("B16"), IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST")), + Subsignal("channel2", Pins("A16"), IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST"))), - ( - "vga", - 0, - Subsignal( - "hsync", - Pins("B12"), - IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST") - ), - - Subsignal( - "vsync", - Pins("A12"), - IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST") - ), - - Subsignal( - "red2", - Pins("C9"), - IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST") - ), - - Subsignal( - "red1", - Pins("B9"), - IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST") - ), - - Subsignal( - "red0", - Pins("A9"), - IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST") - ), - - Subsignal( - "green2", - Pins("C11"), - IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST") - ), - - Subsignal( - "green1", - Pins("A10"), - IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST") - ), - - Subsignal( - "green0", - Pins("C10"), - IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST") - ), - - Subsignal( - "blue2", - Pins("A11"), - IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST") - ), - - Subsignal( - "blue1", - Pins("B11"), - IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST") - ) - ) + ("vga_out", 0, + Subsignal("hsync", Pins("B12"), IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST")), + Subsignal("vsync", Pins("A12"), IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST")), + Subsignal("r", Pins("A9 B9 C9"), IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST")), + Subsignal("g", Pins("C10 A10 C11"), IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST")), + Subsignal("b", Pins("B11 A11"), IOStandard("LVCMOS33"), + Misc("DRIVE=8,SLEW=FAST"))) ] _connectors = [ From 6468fa3db4094cb3201208166fa2a7b2ccc572fe Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 14 Jul 2015 12:53:43 -0600 Subject: [PATCH 4/5] xilinx: ensure we chdir() back after build --- mibuild/xilinx/ise.py | 71 ++++++++++++++++++++++--------------------- 1 file changed, 36 insertions(+), 35 deletions(-) diff --git a/mibuild/xilinx/ise.py b/mibuild/xilinx/ise.py index 6edd3dc2a..50c659c1f 100644 --- a/mibuild/xilinx/ise.py +++ b/mibuild/xilinx/ise.py @@ -163,9 +163,6 @@ class XilinxISEToolchain: def build(self, platform, fragment, build_dir="build", build_name="top", ise_path=_default_ise_path(), source=_default_source(), run=True, mode="xst"): - tools.mkdir_noerror(build_dir) - os.chdir(build_dir) - if not isinstance(fragment, _Fragment): fragment = fragment.get_fragment() platform.finalize(fragment) @@ -174,40 +171,44 @@ class XilinxISEToolchain: vns = None - if mode == "xst" or mode == "yosys": - v_output = platform.get_verilog(fragment) - vns = v_output.ns - named_sc, named_pc = platform.resolve_signals(vns) - v_file = build_name + ".v" - v_output.write(v_file) - sources = platform.sources | {(v_file, "verilog", "work")} - if mode == "xst": - _build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt) - isemode = "xst" - else: - _run_yosys(platform.device, sources, platform.verilog_include_paths, build_name) + tools.mkdir_noerror(build_dir) + cwd = os.getcwd() + os.chdir(build_dir) + try: + if mode == "xst" or mode == "yosys": + v_output = platform.get_verilog(fragment) + vns = v_output.ns + named_sc, named_pc = platform.resolve_signals(vns) + v_file = build_name + ".v" + v_output.write(v_file) + sources = platform.sources | {(v_file, "verilog", "work")} + if mode == "xst": + _build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt) + isemode = "xst" + else: + _run_yosys(platform.device, sources, platform.verilog_include_paths, build_name) + isemode = "edif" + ngdbuild_opt += "-p " + platform.device + + if mode == "mist": + from mist import synthesize + synthesize(fragment, platform.constraint_manager.get_io_signals()) + + if mode == "edif" or mode == "mist": + e_output = platform.get_edif(fragment) + vns = e_output.ns + named_sc, named_pc = platform.resolve_signals(vns) + e_file = build_name + ".edif" + e_output.write(e_file) isemode = "edif" - ngdbuild_opt += "-p " + platform.device - if mode == "mist": - from mist import synthesize - synthesize(fragment, platform.constraint_manager.get_io_signals()) - - if mode == "edif" or mode == "mist": - e_output = platform.get_edif(fragment) - vns = e_output.ns - named_sc, named_pc = platform.resolve_signals(vns) - e_file = build_name + ".edif" - e_output.write(e_file) - isemode = "edif" - - tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc)) - if run: - _run_ise(build_name, ise_path, source, isemode, - ngdbuild_opt, self.bitgen_opt, self.ise_commands, - self.map_opt, self.par_opt) - - os.chdir("..") + tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc)) + if run: + _run_ise(build_name, ise_path, source, isemode, + ngdbuild_opt, self.bitgen_opt, self.ise_commands, + self.map_opt, self.par_opt) + finally: + os.chdir(cwd) return vns From 09b33346beb38463316c68d6d57d91841e160695 Mon Sep 17 00:00:00 2001 From: numato Date: Tue, 14 Jul 2015 12:24:18 -0600 Subject: [PATCH 5/5] Removed drive strength constraints on VGA/Audio signals --- mibuild/platforms/mimasv2.py | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/mibuild/platforms/mimasv2.py b/mibuild/platforms/mimasv2.py index e31950b7b..fd8465692 100644 --- a/mibuild/platforms/mimasv2.py +++ b/mibuild/platforms/mimasv2.py @@ -89,21 +89,21 @@ _io = [ ("audio", 0, Subsignal("channel1", Pins("B16"), IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST")), + Misc("SLEW=FAST")), Subsignal("channel2", Pins("A16"), IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST"))), + Misc("SLEW=FAST"))), ("vga_out", 0, - Subsignal("hsync", Pins("B12"), IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST")), - Subsignal("vsync", Pins("A12"), IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST")), + Subsignal("hsync_n", Pins("B12"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST")), + Subsignal("vsync_n", Pins("A12"), IOStandard("LVCMOS33"), + Misc("SLEW=FAST")), Subsignal("r", Pins("A9 B9 C9"), IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST")), + Misc("SLEW=FAST")), Subsignal("g", Pins("C10 A10 C11"), IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST")), + Misc("SLEW=FAST")), Subsignal("b", Pins("B11 A11"), IOStandard("LVCMOS33"), - Misc("DRIVE=8,SLEW=FAST"))) + Misc("SLEW=FAST"))) ] _connectors = [