From e2cf45b8a9ec58abe8a2ad0ab16ab73de45dbffb Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Fri, 19 Apr 2019 13:04:57 +0800 Subject: [PATCH] cpu: vexriscv: allow cpu_reset_address to be overridden Allow the cpu_reset_address value to be overridden, for example allowing it to be a signal. That way the reset address can be modified after synthesis, in dual-core or debug situations. Signed-off-by: Sean Cross --- litex/soc/cores/cpu/vexriscv/core.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 1edcc3f7b..db05e1fd4 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -21,6 +21,7 @@ class VexRiscv(Module, AutoCSR): self.reset = Signal() self.ibus = ibus = wishbone.Interface() self.dbus = dbus = wishbone.Interface() + self.cpu_reset_address = cpu_reset_address self.interrupt = Signal(32) @@ -28,7 +29,7 @@ class VexRiscv(Module, AutoCSR): i_clk=ClockSignal(), i_reset=ResetSignal() | self.reset, - i_externalResetVector=cpu_reset_address, + i_externalResetVector=self.cpu_reset_address, i_externalInterruptArray=self.interrupt, i_timerInterrupt=0,