From 4a29e2403c5d37747fc847a21f5aa9bfcd76014c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 29 Mar 2021 11:22:31 +0200 Subject: [PATCH] integration/soc/add_sdram: Directly use main_ram mem_map mapping if available. --- litex/soc/integration/soc.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index cafa8c404..f6b384cb6 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -1192,7 +1192,7 @@ class LiteXSoC(SoC): self.bus.add_master(name="jtagbone", master=self.jtagbone.wishbone) # Add SDRAM ------------------------------------------------------------------------------------ - def add_sdram(self, name, phy, module, origin, size=None, with_bist=False, with_soc_interconnect=True, + def add_sdram(self, name, phy, module, origin=None, size=None, with_bist=False, with_soc_interconnect=True, l2_cache_size = 8192, l2_cache_min_data_width = 128, l2_cache_reverse = True, @@ -1250,7 +1250,7 @@ class LiteXSoC(SoC): sdram_size = min(sdram_size, size) # Add SDRAM region. - self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size)) + self.bus.add_region("main_ram", SoCRegion(origin=self.mem_map.get("main_ram", origin), size=sdram_size)) # Add CPU's direct memory buses (if not already declared) ---------------------------------- if hasattr(self.cpu, "add_memory_buses"):