From 4abb3715d991698574859d166dc96568c566c364 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 26 Mar 2020 09:45:19 +0100 Subject: [PATCH] targets/add_constant: avoid specifying value when value is None (=default). --- litex/boards/targets/kcu105.py | 3 ++- litex/boards/targets/versa_ecp5.py | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index 30ff747e7..6e90ec47b 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -67,7 +67,8 @@ class BaseSoC(SoCCore): iodelay_clk_freq = 200e6, cmd_latency = 0) self.add_csr("ddrphy") - self.add_constant("USDDRPHY", None) + self.add_constant("USDDRPHY") + self.add_constant("USDDRPHY_DEBUG") self.add_sdram("sdram", phy = self.ddrphy, module = EDY4016A(sys_clk_freq, "1:4"), diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index 0669e2747..216d7bb39 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -87,7 +87,7 @@ class BaseSoC(SoCCore): platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") - self.add_constant("ECP5DDRPHY", None) + self.add_constant("ECP5DDRPHY") self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.add_sdram("sdram", phy = self.ddrphy,