From 4ada2ead05c0cf11a8591579545ad88a4208d423 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 12 Mar 2013 15:58:39 +0100 Subject: [PATCH] fhdl/specials/Memory: automatic name# --- migen/fhdl/specials.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py index e3c5099e5..ad78a488a 100644 --- a/migen/fhdl/specials.py +++ b/migen/fhdl/specials.py @@ -1,6 +1,6 @@ from migen.fhdl.structure import * from migen.fhdl.tools import list_signals, value_bits_sign - +from migen.fhdl.tracer import get_obj_var_name from migen.fhdl.verilog import _printexpr as verilog_printexpr class Special(HUID): @@ -180,13 +180,13 @@ class _MemoryPort: self.clock_domain = clock_domain class Memory(Special): - def __init__(self, width, depth, init=None, name="mem"): + def __init__(self, width, depth, init=None, name=None): Special.__init__(self) self.width = width self.depth = depth self.ports = [] self.init = init - self.name_override = name + self.name_override = get_obj_var_name(name, "mem") def get_port(self, write_capable=False, async_read=False, has_re=False, we_granularity=0, mode=WRITE_FIRST,