diff --git a/litex/build/osfpga/osfpga.py b/litex/build/osfpga/osfpga.py
index 910fea884..42f3cb0e5 100644
--- a/litex/build/osfpga/osfpga.py
+++ b/litex/build/osfpga/osfpga.py
@@ -22,6 +22,7 @@ class OSFPGAToolchain(GenericToolchain):
     attr_translate = {}
 
     def __init__(self, toolchain):
+        super().__init__()
         self.toolchain = toolchain
         self.clocks    = dict()
 
@@ -36,7 +37,7 @@ class OSFPGAToolchain(GenericToolchain):
         sdc = []
         for clk, period in sorted(self.clocks.items(), key=lambda x: x[0].duid):
             sdc.append(f"create_clock -name {vns.get_name(clk)} -period {str(period)} [get_ports {{{vns.get_name(clk)}}}]")
-        with open(f"{build_name}.sdc", "w") as f:
+        with open(f"{self._build_name}.sdc", "w") as f:
             f.write("\n".join(sdc))
         return (self._build_name + ".sdc", "SDC")
 
@@ -53,7 +54,7 @@ class OSFPGAToolchain(GenericToolchain):
 
         # Add Include Path.
         tcl.append("add_include_path ./")
-        for include_path in platform.verilog_include_paths:
+        for include_path in self.platform.verilog_include_paths:
             tcl.append(f"add_include_path {include_path}")
 
         # Add Sources.
diff --git a/litex/build/osfpga/test_blinky.py b/litex/build/osfpga/test_blinky.py
index 89feb2bd3..7dd79f3ba 100755
--- a/litex/build/osfpga/test_blinky.py
+++ b/litex/build/osfpga/test_blinky.py
@@ -22,7 +22,7 @@ _io = [
 
 class Platform(OSFPGAPlatform):
     def __init__(self):
-        OSFPGAPlatform.__init__(self, device="test", toolchain="raptor", io=_io)
+        OSFPGAPlatform.__init__(self, device="gemini", toolchain="raptor", io=_io)
 
 # Minimal Design -----------------------------------------------------------------------------------
 
diff --git a/litex/build/osfpga/test_soc.py b/litex/build/osfpga/test_soc.py
index 4429a0af4..54b0ca8e3 100755
--- a/litex/build/osfpga/test_soc.py
+++ b/litex/build/osfpga/test_soc.py
@@ -29,7 +29,7 @@ _io = [
 ]
 
 class Platform(OSFPGAPlatform):
-    def __init__(self, toolchain="foedag", device="mpw1"):
+    def __init__(self, toolchain="raptor", device="gemini"):
         OSFPGAPlatform.__init__(self, device=device, toolchain=toolchain, io=_io)
 
 # BaseSoC ------------------------------------------------------------------------------------------
@@ -49,8 +49,8 @@ def main():
     parser = LiteXSoCArgumentParser(description="LiteX Test SoC on OS-FPGA")
     target_group = parser.add_argument_group(title="Target options")
     target_group.add_argument("--build",     action="store_true", help="Build design.")
-    target_group.add_argument("--toolchain", default="foedag",    help="FPGA toolchain.")
-    target_group.add_argument("--device",    default="mpw1",      help="FPGA device.")
+    target_group.add_argument("--toolchain", default="raptor",    help="FPGA toolchain.")
+    target_group.add_argument("--device",    default="gemini",    help="FPGA device.")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()