From 4b3f147fc8b20651cb3b9be3e55f0158ce83c308 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 17 May 2024 12:57:29 +0200 Subject: [PATCH] CHANGES: Update. --- CHANGES.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/CHANGES.md b/CHANGES.md index 28c53e641..f2bc720bd 100644 --- a/CHANGES.md +++ b/CHANGES.md @@ -12,6 +12,7 @@ - litedram/frontend/avalon : Fixed and cleaned-up. - litex_sim/video : Fixed pixel format to RGBA. - build/xilinx/common : Fixed missing clk parameter on XilinxSDRTristateImpl. + - soc/interconnect : Fixed CSR/LiteXModule issue on WishboneSRAM/AXILiteSRAM. [> Added -------- @@ -38,6 +39,9 @@ - cores/hyperbus : Added latency configuration and variable latency support. - cpu/cv32e41p : Added ISR support. - litesdcard : Improved SDPHYClocker (Timings). + - cpu/vexriscv_smp : Added baremetal IRQ support. + - cpu/naxriscv : Added baremetal IRQ support. + - cpu/zynqmp : Added Ethernet, UART, I2C support and improved AXI Master. [> Changed ----------