From 4b4fc7c6c08c05b24156dc1bde50767afa8cbe2d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 25 Jan 2023 12:19:10 +0100 Subject: [PATCH] cores/spi_flash: On Ultrascale: CS/DI/DO also need to be access through STARTUPE3, untested yet. --- litex/soc/cores/spi_flash.py | 78 +++++++++++++++++++++--------------- 1 file changed, 46 insertions(+), 32 deletions(-) diff --git a/litex/soc/cores/spi_flash.py b/litex/soc/cores/spi_flash.py index b7da04711..922cf90dc 100644 --- a/litex/soc/cores/spi_flash.py +++ b/litex/soc/cores/spi_flash.py @@ -6,24 +6,26 @@ from migen import * +from litex.gen import LiteXModule + from litex.soc.interconnect.csr import * from litex.soc.cores.spi import SPIMaster # Xilinx 7-Series FPGAs SPI Flash (non-memory-mapped) ---------------------------------------------- -class S7SPIFlash(Module, AutoCSR): +class S7SPIFlash(LiteXModule): def __init__(self, pads, sys_clk_freq, spi_clk_freq=25e6): - self.submodules.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq) + self.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq) self.specials += Instance("STARTUPE2", - i_CLK = 0, - i_GSR = 0, - i_GTS = 0, - i_KEYCLEARB = 0, - i_PACK = 0, - i_USRCCLKO = spi.pads.clk, - i_USRCCLKTS = 0, - i_USRDONEO = 1, - i_USRDONETS = 1 + i_CLK = 0, + i_GSR = 0, + i_GTS = 0, + i_KEYCLEARB = 0, + i_PACK = 0, + i_USRCCLKO = spi.pads.clk, + i_USRCCLKTS = 0, + i_USRDONEO = 1, + i_USRDONETS = 1, ) if hasattr(pads, "vpp"): pads.vpp.reset = 1 @@ -38,29 +40,41 @@ class S7SPIFlash(Module, AutoCSR): # Xilinx Ultrascale FPGAs SPI Flash (non-memory-mapped) -------------------------------------------- -class USSPIFlash(Module, AutoCSR): - def __init__(self, pads, sys_clk_freq, spi_clk_freq=25e6): - self.submodules.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq) - self.specials += Instance("STARTUPE3", - i_GSR = 0, - i_GTS = 0, - i_KEYCLEARB = 0, - i_PACK = 0, - i_USRCCLKO = spi.pads.clk, - i_USRCCLKTS = 0, - i_USRDONEO = 1, - i_USRDONETS = 1 - ) - if hasattr(pads, "vpp"): - pads.vpp.reset = 1 - if hasattr(pads, "hold"): - pads.hold.reset = 1 - if hasattr(pads, "cs_n"): - self.comb += pads.cs_n.eq(spi.pads.cs_n) +class USSPIFlash(LiteXModule): + def __init__(self, sys_clk_freq, spi_clk_freq=25e6): + self.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq) + spi_dts = Signal(4) + spi_do = Signal(4) + spi_di = Signal(4) self.comb += [ - pads.mosi.eq(spi.pads.mosi), - spi.pads.miso.eq(pads.miso) + # D0: MOSI (Output). + spi_dts[0].eq(0), + spi_do[0].eq(spi.pads.mosi), + # D1: MISO (Input). + spi_dts[1].eq(1), + spi.pads.miso.eq(spi_di[1]), + # D2: Vpp (Output). + spi_dts[2].eq(0), + spi_do[2].eq(1), + # D3: Hold (Input). + spi_dts[3].eq(0), + spi_do[3].eq(1), ] + self.specials += Instance("STARTUPE3", + i_GSR = 0, + i_GTS = 0, + i_KEYCLEARB = 0, + i_PACK = 0, + i_USRCCLKO = spi.pads.clk, + i_USRCCLKTS = 0, + i_USRDONEO = 1, + i_USRDONETS = 1, + i_FCSBTS = 0, + i_FCSBO = spi.pads.cs_n, + i_DTS = spi_dts, + i_DO = spi_do, + o_DI = spi_di, + ) # Lattice ECP5 FPGAs SPI Flash (non-memory-mapped) -------------------------------------------------