diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index dd3d32630..fe76b2ec6 100644
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -121,7 +121,7 @@ class XilinxMultiRegImpl(MultiRegImpl):
 class XilinxMultiReg:
 	@staticmethod
 	def lower(dr):
-		return XilinxMultiRegImpl(dr.i, dr.idomain, dr.o, dr.odomain, dr.n)
+		return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
 
 class XilinxISEPlatform(GenericPlatform):
 	def get_verilog(self, *args, special_overrides=dict(), **kwargs):