From 4bf789eab97452c8928e731adf58851f0b06e875 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 1 Mar 2019 09:16:48 +0100
Subject: [PATCH] soc/software/bios/boot: add vexriscv workaround

Flushing icache was working correctly on previous version of Vexriscv, understand
why it's no longer the case.
---
 litex/soc/software/bios/boot.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c
index e6e0ce246..473b99584 100644
--- a/litex/soc/software/bios/boot.c
+++ b/litex/soc/software/bios/boot.c
@@ -25,7 +25,10 @@ static void __attribute__((noreturn)) boot(unsigned int r1, unsigned int r2, uns
 	uart_sync();
 	irq_setmask(0);
 	irq_setie(0);
+/* FIXME: understand why flushing icache on Vexriscv make boot fail  */
+#ifndef __vexriscv__
 	flush_cpu_icache();
+#endif
 	flush_cpu_dcache();
 #ifdef L2_SIZE
 	flush_l2_cache();