From 4c26dbe98f826da1732dc0bd99a48e3f7cfd43c4 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 26 Apr 2021 18:37:40 +0200
Subject: [PATCH] cores/cpu/microwatt: Re-map csr/xics and keep the lower
 128MBs for the SoC IO auto-allocation.

---
 litex/soc/cores/cpu/microwatt/core.py | 7 ++++---
 litex/soc/integration/soc.py          | 2 +-
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py
index 953db7569..4d1fed0d4 100644
--- a/litex/soc/cores/cpu/microwatt/core.py
+++ b/litex/soc/cores/cpu/microwatt/core.py
@@ -39,9 +39,10 @@ class Microwatt(CPU):
     @property
     def mem_map(self):
         return {
-            "csr":      0xc0000000,
-            "xicsicp":  0xc3ff0000,
-            "xicsics":  0xc3ff1000
+            # Keep the lower 128MBs for SoC IOs auto-allocation.
+            "csr":      0xc8000000,
+            "xicsicp":  0xcbff0000,
+            "xicsics":  0xcbff1000,
         }
 
     # GCC Flags.
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 19a41cc37..276bb91d8 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -233,7 +233,7 @@ class SoCBusHandler(Module):
         for _, search_region in search_regions.items():
             origin = search_region.origin
             while (origin + size) < (search_region.origin + search_region.size_pow2):
-                # Create a Candicate.
+                # Create a Candidate.
                 candidate = SoCRegion(origin=origin, size=size, cached=cached)
                 overlap   = False
                 # Check Candidate does not overlap with allocated existing regions.