diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
index a54680462..9ee678761 100644
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@@ -42,7 +42,7 @@ class RS232ClkPhaseAccum(Module):
     def __init__(self, tuning_word, mode="tx"):
         assert mode in ["tx", "rx"]
         self.enable = Signal()
-        self.tick   = Signal(32)
+        self.tick   = Signal()
 
         # # #