From 4c8184fbb6f9822cb682583aea8475acce93745b Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sun, 20 Jun 2021 08:58:45 +0200
Subject: [PATCH] cores/uart: Fix refactoring typo (tick is a 1-bit Signal),
 thanks @tnt.

---
 litex/soc/cores/uart.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
index a54680462..9ee678761 100644
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@@ -42,7 +42,7 @@ class RS232ClkPhaseAccum(Module):
     def __init__(self, tuning_word, mode="tx"):
         assert mode in ["tx", "rx"]
         self.enable = Signal()
-        self.tick   = Signal(32)
+        self.tick   = Signal()
 
         # # #