From 4ca66bbee68cb5218f065630e2670711d59f9c2e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 28 Feb 2024 19:10:07 +0100 Subject: [PATCH] interconnect/wishbone/Remapper: Fix src_adr/dst_adr signal size. --- litex/soc/interconnect/wishbone.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py index 7b8d28af1..943263f93 100644 --- a/litex/soc/interconnect/wishbone.py +++ b/litex/soc/interconnect/wishbone.py @@ -168,8 +168,8 @@ class Remapper(Module): }[master.addressing] # Apply Address Regions Remapping. for src_region, dst_region in zip(src_regions, dst_regions): - src_adr = Signal.like(master.adr) - dst_adr = Signal.like(master.adr) + src_adr = Signal.like(master.adr + adr_shift + 1) + dst_adr = Signal.like(master.adr + adr_shift + 1) active = Signal() self.comb += [ src_adr.eq(adr_remap << adr_shift),