From 4ccf9f487d99b4fc23e59fb18b8658c5d936b3c8 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 26 Oct 2022 17:27:15 +1030 Subject: [PATCH] microwatt: Fix irq variant The vhd2v conversion missed some things that are only run when building the irq variant. Signed-off-by: Joel Stanley --- litex/soc/cores/cpu/microwatt/core.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py index c613d4783..e65c76e10 100644 --- a/litex/soc/cores/cpu/microwatt/core.py +++ b/litex/soc/cores/cpu/microwatt/core.py @@ -306,8 +306,7 @@ class XICSSlave(Module, AutoCSR): # Add VHDL sources. self.add_sources(platform, use_ghdl_yosys_plugin="ghdl" in self.variant) - @staticmethod - def add_sources(platform, use_ghdl_yosys_plugin=False): + def add_sources(self, platform, use_ghdl_yosys_plugin=False): sources = [ # Common / Types / Helpers "decode_types.vhdl", @@ -323,8 +322,6 @@ class XICSSlave(Module, AutoCSR): cdir = os.path.dirname(__file__) self.ics_vhd2v_converter.add_sources(sdir, *sources) self.ics_vhd2v_converter.add_source(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl")) - self.icp_vhd2v_converter.add_sources(sdir, *sources) - self.icp_vhd2v_converter.add_source(os.path.join(os.path.dirname(__file__), "xics_wrapper.vhdl")) def do_finalize(self): self.specials += Instance("xics_icp_wrapper", **self.icp_params)