From 69177c92519a3b6d3c495e2feafb1134215c07d4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 8 Oct 2020 19:38:57 +0200 Subject: [PATCH 1/8] software/liblitesdram: add initial support for write leveling bitslip (configurable via bios commands). --- litex/soc/software/bios/cmds/cmd_litedram.c | 64 ++++++++++++++++++++- litex/soc/software/liblitedram/sdram.c | 45 ++++++++++++--- litex/soc/software/liblitedram/sdram.h | 2 + 3 files changed, 102 insertions(+), 9 deletions(-) diff --git a/litex/soc/software/bios/cmds/cmd_litedram.c b/litex/soc/software/bios/cmds/cmd_litedram.c index 1d9d51997..b4f804d57 100644 --- a/litex/soc/software/bios/cmds/cmd_litedram.c +++ b/litex/soc/software/bios/cmds/cmd_litedram.c @@ -165,7 +165,7 @@ static void sdram_rst_dat_delay_handler(int nb_params, char **params) sdram_write_leveling_rst_dat_delay(module, 1); sdram_software_control_off(); } -define_command(sdram_rst_dat_delay, sdram_rst_dat_delay_handler, "Force write leveling Dat delay", LITEDRAM_CMDS); +define_command(sdram_rst_dat_delay, sdram_rst_dat_delay_handler, "Reset write leveling Dat delay", LITEDRAM_CMDS); #endif /** @@ -198,7 +198,67 @@ static void sdram_force_dat_delay_handler(int nb_params, char **params) sdram_write_leveling_force_dat_delay(module, taps, 1); sdram_software_control_off(); } -define_command(sdram_force_dat_delay, sdram_force_dat_delay_handler, "Reset write leveling Dat delay", LITEDRAM_CMDS); +define_command(sdram_force_dat_delay, sdram_force_dat_delay_handler, "Force write leveling Dat delay", LITEDRAM_CMDS); +#endif + +/** + * Command "sdram_rst_bitslip" + * + * Reset write leveling Bitslip + * + */ +#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE) +static void sdram_rst_bitslip_handler(int nb_params, char **params) +{ + char *c; + int module; + if (nb_params < 1) { + printf("sdram_rst_bitslip "); + return; + } + module = strtoul(params[0], &c, 0); + if (*c != 0) { + printf("Incorrect module"); + return; + } + sdram_software_control_on(); + sdram_write_leveling_rst_bitslip(module, 1); + sdram_software_control_off(); +} +define_command(sdram_rst_bitslip, sdram_rst_bitslip_handler, "Reset write leveling Bitslip", LITEDRAM_CMDS); +#endif + +/** + * Command "sdram_force_bitslip" + * + * Force write leveling Bitslip + * + */ +#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE) +static void sdram_force_bitslip_handler(int nb_params, char **params) +{ + char *c; + int module; + int bitslip; + if (nb_params < 2) { + printf("sdram_force_bitslip "); + return; + } + module = strtoul(params[0], &c, 0); + if (*c != 0) { + printf("Incorrect module"); + return; + } + bitslip = strtoul(params[1], &c, 0); + if (*c != 0) { + printf("Incorrect bitslip"); + return; + } + sdram_software_control_on(); + sdram_write_leveling_force_bitslip(module, bitslip, 1); + sdram_software_control_off(); +} +define_command(sdram_force_bitslip, sdram_force_bitslip_handler, "Force write leveling Bitslip", LITEDRAM_CMDS); #endif #endif diff --git a/litex/soc/software/liblitedram/sdram.c b/litex/soc/software/liblitedram/sdram.c index 852c37104..5cf6cb387 100644 --- a/litex/soc/software/liblitedram/sdram.c +++ b/litex/soc/software/liblitedram/sdram.c @@ -243,6 +243,7 @@ void sdram_mode_register_write(char reg, int value) { int _sdram_write_leveling_cmd_scan = 1; int _sdram_write_leveling_cmd_delay = 0; int _sdram_write_leveling_dat_delays[16]; +int _sdram_write_leveling_bitslips[16]; static void sdram_write_leveling_on(void) { @@ -305,6 +306,18 @@ void sdram_write_leveling_force_dat_delay(int module, int taps, int show) { printf("Forcing Dat delay of module %d to %d taps\n", module, taps); } +void sdram_write_leveling_rst_bitslip(int module, int show) { + _sdram_write_leveling_bitslips[module] = -1; + if (show) + printf("Reseting Bitslip of module %d\n", module); +} + +void sdram_write_leveling_force_bitslip(int module, int bitslip, int show) { + _sdram_write_leveling_bitslips[module] = bitslip; + if (show) + printf("Forcing Bitslip of module %d to %d\n", module, bitslip); +} + static void sdram_write_leveling_rst_delay(int module) { #ifdef SDRAM_PHY_WRITE_LEVELING_REINIT int i; @@ -506,8 +519,25 @@ int sdram_write_leveling(void) int cdly_range_start; int cdly_range_end; int cdly_range_step; + int i, j; + /* Configure write bitslips */ + for (i=0; i<16; i++) { + /* sel module */ + ddrphy_dly_sel_write(1 << i); + /* rst bitslip */ + ddrphy_wdly_dq_bitslip_rst_write(1); + /* set bitslip */ + if (_sdram_write_leveling_bitslips[i] >= 0) { + for (j=0; j<_sdram_write_leveling_bitslips[i]; j++) { + ddrphy_wdly_dq_bitslip_write(1); + } + } + /* unsel module */ + ddrphy_dly_sel_write(0); + } + if (_sdram_write_leveling_cmd_scan) { printf(" Cmd/Clk scan:\n"); @@ -580,7 +610,7 @@ static void sdram_read_leveling_rst_delay(int module) { #ifdef SDRAM_PHY_ECP5DDRPHY /* Sync all DQSBUFM's, By toggling all dly_sel (DQSBUFM.PAUSE) lines. */ - ddrphy_dly_sel_write(0xFF); + ddrphy_dly_sel_write(0xff); ddrphy_dly_sel_write(0); #endif } @@ -597,7 +627,7 @@ static void sdram_read_leveling_inc_delay(int module) { #ifdef SDRAM_PHY_ECP5DDRPHY /* Sync all DQSBUFM's, By toggling all dly_sel (DQSBUFM.PAUSE) lines. */ - ddrphy_dly_sel_write(0xFF); + ddrphy_dly_sel_write(0xff); ddrphy_dly_sel_write(0); #endif } @@ -607,7 +637,7 @@ static void sdram_read_leveling_rst_bitslip(char m) /* sel module */ ddrphy_dly_sel_write(1 << m); - /* inc delay */ + /* rst delay */ ddrphy_rdly_dq_bitslip_rst_write(1); /* unsel module */ @@ -675,9 +705,9 @@ static int sdram_read_leveling_scan_module(int module, int bitslip) command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA); cdelay(15); for(p=0;p Date: Fri, 9 Oct 2020 15:30:52 +0200 Subject: [PATCH 2/8] software/liblitedram: add functions to simplify read_leveling and do the test with 2 seeds. Doing the test with 2 seeds prevents the test to success if previous content in DRAM was still the expected one (ex after a sdram_cal command that succeded). --- litex/soc/software/liblitedram/sdram.c | 194 ++++++++++--------------- 1 file changed, 78 insertions(+), 116 deletions(-) diff --git a/litex/soc/software/liblitedram/sdram.c b/litex/soc/software/liblitedram/sdram.c index 5cf6cb387..2a9e850a7 100644 --- a/litex/soc/software/liblitedram/sdram.c +++ b/litex/soc/software/liblitedram/sdram.c @@ -1,5 +1,5 @@ -// This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq // This file is Copyright (c) 2013-2020 Florent Kermarrec +// This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq // This file is Copyright (c) 2018 Chris Ballance // This file is Copyright (c) 2018 Dolu1990 // This file is Copyright (c) 2019 Gabriel L. Somlo @@ -657,65 +657,90 @@ static void sdram_read_leveling_inc_bitslip(char m) ddrphy_dly_sel_write(0); } -static int sdram_read_leveling_scan_module(int module, int bitslip) -{ - unsigned int prv; - unsigned char prs[SDRAM_PHY_PHASES][DFII_PIX_DATA_BYTES]; - unsigned char tst[DFII_PIX_DATA_BYTES]; - int p, i; - int score; - - /* Generate pseudo-random sequence */ - prv = 42; - for(p=0;p> module) & 0x1) != 1) + return 0; +#endif + + return 1; +} + +static int sdram_read_leveling_scan_module(int module, int bitslip) +{ + int i; + int score; + + /* Activate */ + sdram_activate_test_row(); + + /* Check test pattern for each delay value */ + score = 0; printf(" m%d, b%d: |", module, bitslip); sdram_read_leveling_rst_delay(module); for(i=0;i 32 show = (i%16 == 0); #endif -#ifdef SDRAM_PHY_ECP5DDRPHY - ddrphy_burstdet_clr_write(1); -#endif - command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA); - cdelay(15); - for(p=0;p> module) & 0x1) != 1) - working = 0; -#endif + working = sdram_write_read_check_test_pattern(module, 42); + working &= sdram_write_read_check_test_pattern(module, 43); if (show) printf("%d", working); score += working; @@ -724,72 +749,28 @@ static int sdram_read_leveling_scan_module(int module, int bitslip) printf("| "); /* Precharge */ - sdram_dfii_pi0_address_write(0); - sdram_dfii_pi0_baddress_write(0); - command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS); - cdelay(15); + sdram_precharge_test_row(); return score; } static void sdram_read_leveling_module(int module) { - unsigned int prv; - unsigned char prs[SDRAM_PHY_PHASES][DFII_PIX_DATA_BYTES]; - unsigned char tst[DFII_PIX_DATA_BYTES]; - int p, i; + int i; int working; int delay, delay_min, delay_max; printf("delays: "); - /* Generate pseudo-random sequence */ - prv = 42; - for(p=0;p> module) & 0x1) != 1) - working = 0; -#endif + working = sdram_write_read_check_test_pattern(module, 42); + working &= sdram_write_read_check_test_pattern(module, 43); if(working) break; delay++; @@ -812,24 +793,8 @@ static void sdram_read_leveling_module(int module) /* Find largest working delay */ while(1) { -#ifdef SDRAM_PHY_ECP5DDRPHY - ddrphy_burstdet_clr_write(1); -#endif - command_prd(DFII_COMMAND_CAS|DFII_COMMAND_CS|DFII_COMMAND_RDDATA); - cdelay(15); - working = 1; - for(p=0;p> module) & 0x1) != 1) - working = 0; -#endif + working = sdram_write_read_check_test_pattern(module, 42); + working &= sdram_write_read_check_test_pattern(module, 43); if(!working) break; delay++; @@ -850,10 +815,7 @@ static void sdram_read_leveling_module(int module) sdram_read_leveling_inc_delay(module); /* Precharge */ - sdram_dfii_pi0_address_write(0); - sdram_dfii_pi0_baddress_write(0); - command_p0(DFII_COMMAND_RAS|DFII_COMMAND_WE|DFII_COMMAND_CS); - cdelay(15); + sdram_precharge_test_row(); } #endif /* CSR_DDRPHY_BASE */ @@ -872,11 +834,11 @@ void sdram_read_leveling(void) int best_bitslip; for(module=0; module Date: Fri, 9 Oct 2020 19:13:10 +0200 Subject: [PATCH 3/8] software/liblitedram: add initial write latency calibration. --- litex/soc/software/liblitedram/sdram.c | 97 +++++++++++++++++++------- 1 file changed, 72 insertions(+), 25 deletions(-) diff --git a/litex/soc/software/liblitedram/sdram.c b/litex/soc/software/liblitedram/sdram.c index 2a9e850a7..d75d67f52 100644 --- a/litex/soc/software/liblitedram/sdram.c +++ b/litex/soc/software/liblitedram/sdram.c @@ -519,24 +519,6 @@ int sdram_write_leveling(void) int cdly_range_start; int cdly_range_end; int cdly_range_step; - int i, j; - - - /* Configure write bitslips */ - for (i=0; i<16; i++) { - /* sel module */ - ddrphy_dly_sel_write(1 << i); - /* rst bitslip */ - ddrphy_wdly_dq_bitslip_rst_write(1); - /* set bitslip */ - if (_sdram_write_leveling_bitslips[i] >= 0) { - for (j=0; j<_sdram_write_leveling_bitslips[i]; j++) { - ddrphy_wdly_dq_bitslip_write(1); - } - } - /* unsel module */ - ddrphy_dly_sel_write(0); - } if (_sdram_write_leveling_cmd_scan) { printf(" Cmd/Clk scan:\n"); @@ -721,7 +703,7 @@ static int sdram_write_read_check_test_pattern(int module, unsigned int seed) { return 1; } -static int sdram_read_leveling_scan_module(int module, int bitslip) +static int sdram_read_leveling_scan_module(int module, int bitslip, int show) { int i; int score; @@ -731,22 +713,24 @@ static int sdram_read_leveling_scan_module(int module, int bitslip) /* Check test pattern for each delay value */ score = 0; - printf(" m%d, b%d: |", module, bitslip); + if (show) + printf(" m%d, b%d: |", module, bitslip); sdram_read_leveling_rst_delay(module); for(i=0;i 32 - show = (i%16 == 0); + _show = (i%16 == 0) & show; #endif working = sdram_write_read_check_test_pattern(module, 42); working &= sdram_write_read_check_test_pattern(module, 43); - if (show) + if (_show) printf("%d", working); score += working; sdram_read_leveling_inc_delay(module); } - printf("| "); + if (show) + printf("| "); /* Precharge */ sdram_precharge_test_row(); @@ -839,7 +823,7 @@ void sdram_read_leveling(void) best_bitslip = 0; for(bitslip=0; bitslip best_score) { @@ -865,6 +849,66 @@ void sdram_read_leveling(void) } } +/*-----------------------------------------------------------------------*/ +/* Write latency calibration */ +/*-----------------------------------------------------------------------*/ + +static void sdram_write_latency_calibration(void) { + int i; + int module; + int bitslip; + int score; + int best_score; + int best_bitslip; + + for(module=0; module best_score) { + best_bitslip = bitslip; + best_score = score; + } + } + + if (_sdram_write_leveling_bitslips[module] < 0) + bitslip = best_bitslip; + else + bitslip = _sdram_write_leveling_bitslips[module]; + printf("m%d:%d ", module, bitslip); + + /* Select best write window */ + ddrphy_dly_sel_write(1 << module); + /* rst bitslip */ + ddrphy_wdly_dq_bitslip_rst_write(1); + for (i=0; i Date: Mon, 12 Oct 2020 10:58:43 +0200 Subject: [PATCH 4/8] software/liblitedram: use 2 cycles increment on write bitslip (for tCK steps). --- litex/soc/software/liblitedram/sdram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/soc/software/liblitedram/sdram.c b/litex/soc/software/liblitedram/sdram.c index d75d67f52..282f9ab86 100644 --- a/litex/soc/software/liblitedram/sdram.c +++ b/litex/soc/software/liblitedram/sdram.c @@ -865,7 +865,7 @@ static void sdram_write_latency_calibration(void) { /* Scan possible write windows */ best_score = 0; best_bitslip = 0; - for(bitslip=0; bitslip Date: Mon, 12 Oct 2020 13:00:44 +0200 Subject: [PATCH 5/8] software/liblitedram/sdram.c: move activate/precharge to sdram_write_read_check_test_pattern, change second seed. --- litex/soc/software/liblitedram/sdram.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/litex/soc/software/liblitedram/sdram.c b/litex/soc/software/liblitedram/sdram.c index 282f9ab86..3273cad3b 100644 --- a/litex/soc/software/liblitedram/sdram.c +++ b/litex/soc/software/liblitedram/sdram.c @@ -668,6 +668,9 @@ static int sdram_write_read_check_test_pattern(int module, unsigned int seed) { } } + /* Activate */ + sdram_activate_test_row(); + /* Write pseudo-random sequence */ for(p=0;p 32 _show = (i%16 == 0) & show; #endif - working = sdram_write_read_check_test_pattern(module, 42); - working &= sdram_write_read_check_test_pattern(module, 43); + working = sdram_write_read_check_test_pattern(module, 42); + working &= sdram_write_read_check_test_pattern(module, 84); if (_show) printf("%d", working); score += working; @@ -732,9 +735,6 @@ static int sdram_read_leveling_scan_module(int module, int bitslip, int show) if (show) printf("| "); - /* Precharge */ - sdram_precharge_test_row(); - return score; } @@ -746,15 +746,12 @@ static void sdram_read_leveling_module(int module) printf("delays: "); - /* Activate */ - sdram_activate_test_row(); - /* Find smallest working delay */ delay = 0; sdram_read_leveling_rst_delay(module); while(1) { working = sdram_write_read_check_test_pattern(module, 42); - working &= sdram_write_read_check_test_pattern(module, 43); + working &= sdram_write_read_check_test_pattern(module, 84); if(working) break; delay++; @@ -778,7 +775,7 @@ static void sdram_read_leveling_module(int module) /* Find largest working delay */ while(1) { working = sdram_write_read_check_test_pattern(module, 42); - working &= sdram_write_read_check_test_pattern(module, 43); + working &= sdram_write_read_check_test_pattern(module, 84); if(!working) break; delay++; @@ -797,9 +794,6 @@ static void sdram_read_leveling_module(int module) sdram_read_leveling_rst_delay(module); for(i=0;i<(delay_min+delay_max)/2;i++) sdram_read_leveling_inc_delay(module); - - /* Precharge */ - sdram_precharge_test_row(); } #endif /* CSR_DDRPHY_BASE */ From c596135274fdfb53bbfeca0aa9b5466470b18dc5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 12 Oct 2020 13:52:15 +0200 Subject: [PATCH 6/8] bios/cmd/cmd_litedram: add sdram_test command. --- litex/soc/software/bios/cmds/cmd_litedram.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/litex/soc/software/bios/cmds/cmd_litedram.c b/litex/soc/software/bios/cmds/cmd_litedram.c index b4f804d57..234814e4d 100644 --- a/litex/soc/software/bios/cmds/cmd_litedram.c +++ b/litex/soc/software/bios/cmds/cmd_litedram.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include @@ -40,6 +41,20 @@ static void sdram_cal_handler(int nb_params, char **params) define_command(sdram_cal, sdram_cal_handler, "Calibrate SDRAM", LITEDRAM_CMDS); #endif +/** + * Command "sdram_test" + * + * Test SDRAM + * + */ +#if defined(CSR_SDRAM_BASE) +static void sdram_test_handler(int nb_params, char **params) +{ + memtest((unsigned int *)MAIN_RAM_BASE, MAIN_RAM_SIZE/32); +} +define_command(sdram_test, sdram_test_handler, "Test SDRAM", LITEDRAM_CMDS); +#endif + #ifdef CSR_DDRPHY_RDPHASE_ADDR /** * Command "sdram_force_rdphase" From bc683514752d30281ec8056fb4d50e8002560af8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 12 Oct 2020 15:52:54 +0200 Subject: [PATCH 7/8] software/liblitedram: use SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE flag. --- litex/soc/software/liblitedram/sdram.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/litex/soc/software/liblitedram/sdram.c b/litex/soc/software/liblitedram/sdram.c index 3273cad3b..c8cfbb869 100644 --- a/litex/soc/software/liblitedram/sdram.c +++ b/litex/soc/software/liblitedram/sdram.c @@ -238,12 +238,13 @@ void sdram_mode_register_write(char reg, int value) { /* Write Leveling */ /*-----------------------------------------------------------------------*/ +int _sdram_write_leveling_bitslips[16]; + #ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE int _sdram_write_leveling_cmd_scan = 1; int _sdram_write_leveling_cmd_delay = 0; int _sdram_write_leveling_dat_delays[16]; -int _sdram_write_leveling_bitslips[16]; static void sdram_write_leveling_on(void) { @@ -847,6 +848,8 @@ void sdram_read_leveling(void) /* Write latency calibration */ /*-----------------------------------------------------------------------*/ +#ifdef SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE + static void sdram_write_latency_calibration(void) { int i; int module; @@ -903,6 +906,8 @@ static void sdram_write_latency_calibration(void) { printf("\n"); } +#endif + /*-----------------------------------------------------------------------*/ /* Leveling */ /*-----------------------------------------------------------------------*/ @@ -925,8 +930,10 @@ int sdram_leveling(void) sdram_write_leveling(); #endif +#ifdef SDRAM_PHY_WRITE_LATENCY_CALIBRATION_CAPABLE printf("Write latency calibration:\n"); sdram_write_latency_calibration(); +#endif #ifdef SDRAM_PHY_READ_LEVELING_CAPABLE printf("Read leveling:\n"); From f0abc185e1135c2ba51ec17e6eadb6861b914071 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 12 Oct 2020 17:35:39 +0200 Subject: [PATCH 8/8] targets/sim: update sdram (manual cmd_latency no longer needed). --- litex/boards/targets/genesys2.py | 3 +-- litex/boards/targets/kc705.py | 3 +-- litex/boards/targets/kcu105.py | 3 +-- litex/tools/litex_sim.py | 12 ++++-------- 4 files changed, 7 insertions(+), 14 deletions(-) diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index c10d6fb2d..69cfc2a41 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -63,8 +63,7 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, - sys_clk_freq = sys_clk_freq, - cmd_latency = 1) + sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 15f312eb8..320d0ca78 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -65,8 +65,7 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, - sys_clk_freq = sys_clk_freq, - cmd_latency = 1) + sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index 7a9111d9c..83a4e684f 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -74,8 +74,7 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), memtype = "DDR4", sys_clk_freq = sys_clk_freq, - iodelay_clk_freq = 200e6, - cmd_latency = 1) + iodelay_clk_freq = 200e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index 3d5fbd124..8585b1ed0 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -114,27 +114,23 @@ def get_sdram_phy_settings(memtype, data_width, clk_freq): elif memtype in ["DDR2", "DDR3"]: # Settings from s7ddrphy tck = 2/(2*nphases*clk_freq) - cmd_latency = 0 cl, cwl = get_cl_cw(memtype, tck) cl_sys_latency = get_sys_latency(nphases, cl) - cwl = cwl + cmd_latency cwl_sys_latency = get_sys_latency(nphases, cwl) rdphase = get_sys_phase(nphases, cl_sys_latency, cl) wrphase = get_sys_phase(nphases, cwl_sys_latency, cwl) - read_latency = 2 + cl_sys_latency + 2 + 3 - write_latency = cwl_sys_latency + read_latency = cl_sys_latency + 6 + write_latency = cwl_sys_latency - 1 elif memtype == "DDR4": # Settings from usddrphy tck = 2/(2*nphases*clk_freq) - cmd_latency = 0 cl, cwl = get_cl_cw(memtype, tck) cl_sys_latency = get_sys_latency(nphases, cl) - cwl = cwl + cmd_latency cwl_sys_latency = get_sys_latency(nphases, cwl) rdphase = get_sys_phase(nphases, cl_sys_latency, cl) wrphase = get_sys_phase(nphases, cwl_sys_latency, cwl) - read_latency = 2 + cl_sys_latency + 1 + 3 - write_latency = cwl_sys_latency + read_latency = cl_sys_latency + 5 + write_latency = cwl_sys_latency - 1 sdram_phy_settings = { "nphases": nphases,