From d5a21a7522daf4978c344490983157efd65b3a2e Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 23 Feb 2020 06:54:48 -0800 Subject: [PATCH 01/16] Converting litex to use Python modules. --- litex/data/__init__.py | 2 ++ litex/data/find.py | 13 +++++++++++++ litex/soc/cores/cpu/blackparrot/core.py | 3 ++- litex/soc/cores/cpu/lm32/core.py | 8 ++++---- litex/soc/cores/cpu/microwatt/core.py | 3 ++- litex/soc/cores/cpu/mor1kx/core.py | 1 + litex/soc/cores/cpu/picorv32/core.py | 4 ++-- litex/soc/cores/cpu/rocket/core.py | 4 ++-- litex/soc/cores/cpu/vexriscv/core.py | 3 ++- litex_setup.py | 12 +++++++++++- 10 files changed, 41 insertions(+), 12 deletions(-) create mode 100644 litex/data/__init__.py create mode 100644 litex/data/find.py diff --git a/litex/data/__init__.py b/litex/data/__init__.py new file mode 100644 index 000000000..c9b5ae908 --- /dev/null +++ b/litex/data/__init__.py @@ -0,0 +1,2 @@ +# https://packaging.python.org/guides/packaging-namespace-packages/#pkgutil-style-namespace-packages +__path__ = __import__('pkgutil').extend_path(__path__, __name__) diff --git a/litex/data/find.py b/litex/data/find.py new file mode 100644 index 000000000..da7ed9819 --- /dev/null +++ b/litex/data/find.py @@ -0,0 +1,13 @@ +def find_data(data_type, data_name): + imp = "from litex.data.{} import {} as dm".format(data_type, data_name) + try: + exec(imp) + return dm.data_location + except ImportError as e: + raise ImportError("""\ +litex-data-{dt}-{dn} module not install! Unable to use {dn} {dt}. +{e} + +You can install this by running; + pip install git+https://github.com/litex-hub/litex-data-{dt}-{dn}.git +""".format(dt=data_type, dn=data_name, e=e)) diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py index 897664892..e55e6252b 100644 --- a/litex/soc/cores/cpu/blackparrot/core.py +++ b/litex/soc/cores/cpu/blackparrot/core.py @@ -32,6 +32,7 @@ import os from migen import * +from litex.data.find import find_data from litex.soc.interconnect import axi from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -115,7 +116,7 @@ class BlackParrotRV64(CPU): @staticmethod def add_sources(platform, variant="standard"): - filename = os.path.join(os.path.abspath(os.path.dirname(__file__)), "flist_litex.verilator") + filename = os.path.join(find_data("cpu", "blackparrot"), "flist_litex.verilator") with open(filename) as openfileobject: for line in openfileobject: temp = line diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index 9ef8333b9..75e7ba8cb 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -9,6 +9,7 @@ import os from migen import * +from litex.data.find import find_data from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -96,9 +97,8 @@ class LM32(CPU): @staticmethod def add_sources(platform, variant): - vdir = os.path.join( - os.path.abspath(os.path.dirname(__file__)), "verilog") - platform.add_sources(os.path.join(vdir, "submodule", "rtl"), + vdir = find_data("cpu", "lm32") + platform.add_sources(os.path.join(vdir, "rtl"), "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v", @@ -117,7 +117,7 @@ class LM32(CPU): "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v") - platform.add_verilog_include_path(os.path.join(vdir, "submodule", "rtl")) + platform.add_verilog_include_path(os.path.join(vdir, "rtl")) if variant == "minimal": platform.add_verilog_include_path(os.path.join(vdir, "config_minimal")) elif variant == "lite": diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py index 584ad4450..aa00ee172 100644 --- a/litex/soc/cores/cpu/microwatt/core.py +++ b/litex/soc/cores/cpu/microwatt/core.py @@ -6,6 +6,7 @@ import os from migen import * +from litex.data.find import find_data from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -98,7 +99,7 @@ class Microwatt(CPU): @staticmethod def add_sources(platform): - sdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "sources") + sdir = os.path.join(find_data("cpu", "microwatt"), "sources") platform.add_sources(sdir, # Common / Types / Helpers "decode_types.vhdl", diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index c82b6e55d..4fe41b36c 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -8,6 +8,7 @@ import os from migen import * +from litex.data.find import find_data from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index 304f6c14d..47017ac6b 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -11,6 +11,7 @@ import os from migen import * +from litex.data.find import find_data from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -179,8 +180,7 @@ class PicoRV32(CPU): @staticmethod def add_sources(platform): - vdir = os.path.join( - os.path.abspath(os.path.dirname(__file__)), "verilog") + vdir = find_data("cpu", "picorv32") platform.add_source(os.path.join(vdir, "picorv32.v")) def do_finalize(self): diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index 14bab0f41..dff3fe707 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -33,6 +33,7 @@ import os from migen import * +from litex.data.find import find_data from litex.soc.interconnect import axi from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -238,8 +239,7 @@ class RocketRV64(CPU): @staticmethod def add_sources(platform, variant="standard"): - vdir = os.path.join( - os.path.abspath(os.path.dirname(__file__)), "verilog") + vdir = find_data("cpu", "rocket") platform.add_sources( os.path.join(vdir, "generated-src"), CPU_VARIANTS[variant] + ".v", diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 4e0bbc0a0..42328d199 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -12,6 +12,7 @@ import os from migen import * +from litex.data.find import find_data from litex.soc.interconnect import wishbone from litex.soc.interconnect.csr import * from litex.soc.cores.cpu import CPU @@ -246,7 +247,7 @@ class VexRiscv(CPU, AutoCSR): @staticmethod def add_sources(platform, variant="standard"): cpu_filename = CPU_VARIANTS[variant] + ".v" - vdir = os.path.join(os.path.abspath(os.path.dirname(__file__)), "verilog") + vdir = find_data("cpu", "vexriscv") platform.add_source(os.path.join(vdir, cpu_filename)) def use_external_variant(self, variant_filename): diff --git a/litex_setup.py b/litex_setup.py index 60582955e..ca1d4f49e 100755 --- a/litex_setup.py +++ b/litex_setup.py @@ -18,7 +18,8 @@ repos = [ ("migen", ("https://github.com/m-labs/", True, True)), # LiteX SoC builder - ("litex", ("https://github.com/enjoy-digital/", True, True)), + ('litex-data-software-compiler_rt', ("https://github.com/litex-hub/", False, True)) + ("litex", ("https://github.com/enjoy-digital/", False, True)), # LiteX cores ecosystem ("liteeth", ("https://github.com/enjoy-digital/", False, True)), @@ -34,6 +35,15 @@ repos = [ # LiteX boards support ("litex-boards", ("https://github.com/litex-hub/", False, True)), + + # Optional LiteX data + ('litex-data-cpu-blackparrot', ("https://github.com/litex-hub/", False, True)) + ('litex-data-cpu-mor1kx', ("https://github.com/litex-hub/", False, True)) + ('litex-data-cpu-lm32', ("https://github.com/litex-hub/", False, True)) + ('litex-data-cpu-microwatt', ("https://github.com/litex-hub/", False, True)) + ('litex-data-cpu-picorv32', ("https://github.com/litex-hub/", False, True)) + ('litex-data-cpu-rocket', ("https://github.com/litex-hub/", False, True)) + ('litex-data-misc-tapcfg', ("https://github.com/litex-hub/", False, True)) ] repos = OrderedDict(repos) From 3964565e1572a859be55da17599d0f1b6edba2a0 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 23 Feb 2020 13:38:05 -0800 Subject: [PATCH 02/16] Fixed quotes in `litex_setup.py` --- litex_setup.py | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/litex_setup.py b/litex_setup.py index ca1d4f49e..9de1e7494 100755 --- a/litex_setup.py +++ b/litex_setup.py @@ -37,13 +37,13 @@ repos = [ ("litex-boards", ("https://github.com/litex-hub/", False, True)), # Optional LiteX data - ('litex-data-cpu-blackparrot', ("https://github.com/litex-hub/", False, True)) - ('litex-data-cpu-mor1kx', ("https://github.com/litex-hub/", False, True)) - ('litex-data-cpu-lm32', ("https://github.com/litex-hub/", False, True)) - ('litex-data-cpu-microwatt', ("https://github.com/litex-hub/", False, True)) - ('litex-data-cpu-picorv32', ("https://github.com/litex-hub/", False, True)) - ('litex-data-cpu-rocket', ("https://github.com/litex-hub/", False, True)) - ('litex-data-misc-tapcfg', ("https://github.com/litex-hub/", False, True)) + ("litex-data-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)) + ("litex-data-cpu-mor1kx", ("https://github.com/litex-hub/", False, True)) + ("litex-data-cpu-lm32", ("https://github.com/litex-hub/", False, True)) + ("litex-data-cpu-microwatt", ("https://github.com/litex-hub/", False, True)) + ("litex-data-cpu-picorv32", ("https://github.com/litex-hub/", False, True)) + ("litex-data-cpu-rocket", ("https://github.com/litex-hub/", False, True)) + ("litex-data-misc-tapcfg", ("https://github.com/litex-hub/", False, True)) ] repos = OrderedDict(repos) From 3df6c0c8a21e7ff62724b444f19372970940a619 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 23 Feb 2020 13:39:45 -0800 Subject: [PATCH 03/16] Adding litex-data-software-compiler_rt as a required package. --- setup.py | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/setup.py b/setup.py index 46f8b6eeb..84824a9ad 100755 --- a/setup.py +++ b/setup.py @@ -14,9 +14,20 @@ setup( test_suite="test", license="BSD", python_requires="~=3.6", - install_requires=["migen", "pyserial"], + install_requires=["migen", "pyserial", "litex-data-software-compiler_rt"], packages=find_packages(exclude=("test*", "sim*", "doc*")), include_package_data=True, + platforms=["Any"], + keywords="HDL ASIC FPGA hardware design", + classifiers=[ + "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)", + "Environment :: Console", + "Development Status :: Alpha", + "Intended Audience :: Developers", + "License :: OSI Approved :: BSD License", + "Operating System :: OS Independent", + "Programming Language :: Python", + ], entry_points={ "console_scripts": [ # full names From ac3fd794f922061653ace78c59fdeccb4327e178 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 23 Feb 2020 14:19:12 -0800 Subject: [PATCH 04/16] Adding missing comma. --- litex_setup.py | 16 ++++++++-------- setup.py | 6 +++++- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/litex_setup.py b/litex_setup.py index 9de1e7494..ffd8fd76f 100755 --- a/litex_setup.py +++ b/litex_setup.py @@ -18,7 +18,7 @@ repos = [ ("migen", ("https://github.com/m-labs/", True, True)), # LiteX SoC builder - ('litex-data-software-compiler_rt', ("https://github.com/litex-hub/", False, True)) + ('litex-data-software-compiler_rt', ("https://github.com/litex-hub/", False, True)), ("litex", ("https://github.com/enjoy-digital/", False, True)), # LiteX cores ecosystem @@ -37,13 +37,13 @@ repos = [ ("litex-boards", ("https://github.com/litex-hub/", False, True)), # Optional LiteX data - ("litex-data-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)) - ("litex-data-cpu-mor1kx", ("https://github.com/litex-hub/", False, True)) - ("litex-data-cpu-lm32", ("https://github.com/litex-hub/", False, True)) - ("litex-data-cpu-microwatt", ("https://github.com/litex-hub/", False, True)) - ("litex-data-cpu-picorv32", ("https://github.com/litex-hub/", False, True)) - ("litex-data-cpu-rocket", ("https://github.com/litex-hub/", False, True)) - ("litex-data-misc-tapcfg", ("https://github.com/litex-hub/", False, True)) + ("litex-data-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)), + ("litex-data-cpu-mor1kx", ("https://github.com/litex-hub/", False, True)), + ("litex-data-cpu-lm32", ("https://github.com/litex-hub/", False, True)), + ("litex-data-cpu-microwatt", ("https://github.com/litex-hub/", False, True)), + ("litex-data-cpu-picorv32", ("https://github.com/litex-hub/", False, True)), + ("litex-data-cpu-rocket", ("https://github.com/litex-hub/", False, True)), + ("litex-data-misc-tapcfg", ("https://github.com/litex-hub/", False, True)), ] repos = OrderedDict(repos) diff --git a/setup.py b/setup.py index 84824a9ad..9c7444270 100755 --- a/setup.py +++ b/setup.py @@ -14,7 +14,11 @@ setup( test_suite="test", license="BSD", python_requires="~=3.6", - install_requires=["migen", "pyserial", "litex-data-software-compiler_rt"], + install_requires=[ + "migen", + "pyserial", + "litex-data-software-compiler_rt", + ], packages=find_packages(exclude=("test*", "sim*", "doc*")), include_package_data=True, platforms=["Any"], From 3ae4f8f2de7494411e5278b11dd7db1c0ae7389f Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 23 Feb 2020 14:54:07 -0800 Subject: [PATCH 05/16] Adding missing vexriscv CPU. --- litex_setup.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex_setup.py b/litex_setup.py index ffd8fd76f..ff2777bfa 100755 --- a/litex_setup.py +++ b/litex_setup.py @@ -43,6 +43,7 @@ repos = [ ("litex-data-cpu-microwatt", ("https://github.com/litex-hub/", False, True)), ("litex-data-cpu-picorv32", ("https://github.com/litex-hub/", False, True)), ("litex-data-cpu-rocket", ("https://github.com/litex-hub/", False, True)), + ("litex-data-cpu-vexriscv", ("https://github.com/litex-hub/", False, True)), ("litex-data-misc-tapcfg", ("https://github.com/litex-hub/", False, True)), ] repos = OrderedDict(repos) From 69367f8d4efd07a9aae3e877746939a16e805127 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 23 Feb 2020 14:56:51 -0800 Subject: [PATCH 06/16] Make litex a namespace. --- litex/__init__.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litex/__init__.py b/litex/__init__.py index ca1e6d75b..2454c0e79 100644 --- a/litex/__init__.py +++ b/litex/__init__.py @@ -1,3 +1,6 @@ +# https://packaging.python.org/guides/packaging-namespace-packages/#pkgutil-style-namespace-packages +__path__ = __import__('pkgutil').extend_path(__path__, __name__) + import sys # retro-compat 2019-09-30 From 119985f3532081b82796459cedb685ce9bcd8230 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 23 Feb 2020 14:58:45 -0800 Subject: [PATCH 07/16] Use the current directory you are running. --- litex_setup.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex_setup.py b/litex_setup.py index ff2777bfa..c6389ad66 100755 --- a/litex_setup.py +++ b/litex_setup.py @@ -8,7 +8,8 @@ from collections import OrderedDict import urllib.request -current_path = os.path.dirname(os.path.realpath(__file__)) +current_path = os.path.abspath(os.curdir) + # Repositories ------------------------------------------------------------------------------------- From c96d1e667277809891f0edffbf7c8ff0a3f38848 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 23 Feb 2020 15:29:46 -0800 Subject: [PATCH 08/16] Fix import for data. --- litex/data/find.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/litex/data/find.py b/litex/data/find.py index da7ed9819..1a143b1dc 100644 --- a/litex/data/find.py +++ b/litex/data/find.py @@ -1,7 +1,9 @@ def find_data(data_type, data_name): imp = "from litex.data.{} import {} as dm".format(data_type, data_name) try: - exec(imp) + l = {} + exec(imp, {}, l) + dm = l['dm'] return dm.data_location except ImportError as e: raise ImportError("""\ From 1c1c5bcbda88e5d3ca93e8a7de1dcb3c05b4aa8b Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 23 Feb 2020 16:06:51 -0800 Subject: [PATCH 09/16] Remove submodules. --- .gitmodules | 30 ------------------- litex/build/sim/core/modules/ethernet/tapcfg | 1 - .../cores/cpu/blackparrot/pre-alpha-release | 1 - litex/soc/cores/cpu/lm32/verilog/submodule | 1 - litex/soc/cores/cpu/microwatt/sources | 1 - litex/soc/cores/cpu/minerva/verilog | 1 - litex/soc/cores/cpu/mor1kx/verilog | 1 - litex/soc/cores/cpu/picorv32/verilog | 1 - litex/soc/cores/cpu/rocket/verilog | 1 - litex/soc/cores/cpu/vexriscv/verilog | 1 - litex/soc/software/compiler_rt | 1 - 11 files changed, 40 deletions(-) delete mode 100644 .gitmodules delete mode 160000 litex/build/sim/core/modules/ethernet/tapcfg delete mode 160000 litex/soc/cores/cpu/blackparrot/pre-alpha-release delete mode 160000 litex/soc/cores/cpu/lm32/verilog/submodule delete mode 160000 litex/soc/cores/cpu/microwatt/sources delete mode 160000 litex/soc/cores/cpu/minerva/verilog delete mode 160000 litex/soc/cores/cpu/mor1kx/verilog delete mode 160000 litex/soc/cores/cpu/picorv32/verilog delete mode 160000 litex/soc/cores/cpu/rocket/verilog delete mode 160000 litex/soc/cores/cpu/vexriscv/verilog delete mode 160000 litex/soc/software/compiler_rt diff --git a/.gitmodules b/.gitmodules deleted file mode 100644 index a683f7367..000000000 --- a/.gitmodules +++ /dev/null @@ -1,30 +0,0 @@ -[submodule "litex/soc/cores/cpu/lm32/verilog/submodule"] - path = litex/soc/cores/cpu/lm32/verilog/submodule - url = https://github.com/m-labs/lm32.git -[submodule "litex/soc/cores/cpu/mor1kx/verilog"] - path = litex/soc/cores/cpu/mor1kx/verilog - url = https://github.com/openrisc/mor1kx.git -[submodule "litex/soc/software/compiler_rt"] - path = litex/soc/software/compiler_rt - url = https://github.com/llvm-mirror/compiler-rt -[submodule "litex/soc/cores/cpu/picorv32/verilog"] - path = litex/soc/cores/cpu/picorv32/verilog - url = https://github.com/cliffordwolf/picorv32 -[submodule "litex/build/sim/core/modules/ethernet/tapcfg"] - path = litex/build/sim/core/modules/ethernet/tapcfg - url = https://github.com/enjoy-digital/tapcfg -[submodule "litex/soc/cores/cpu/vexriscv/verilog"] - path = litex/soc/cores/cpu/vexriscv/verilog - url = https://github.com/enjoy-digital/VexRiscv-verilog.git -[submodule "litex/soc/cores/cpu/minerva/verilog"] - path = litex/soc/cores/cpu/minerva/verilog - url = https://github.com/lambdaconcept/minerva -[submodule "litex/soc/cores/cpu/rocket/verilog"] - path = litex/soc/cores/cpu/rocket/verilog - url = https://github.com/enjoy-digital/rocket-litex-verilog -[submodule "litex/soc/cores/cpu/microwatt/sources"] - path = litex/soc/cores/cpu/microwatt/sources - url = https://github.com/antonblanchard/microwatt -[submodule "litex/soc/cores/cpu/blackparrot/pre-alpha-release"] - path = litex/soc/cores/cpu/blackparrot/pre-alpha-release - url = https://github.com/enjoy-digital/black-parrot.git diff --git a/litex/build/sim/core/modules/ethernet/tapcfg b/litex/build/sim/core/modules/ethernet/tapcfg deleted file mode 160000 index bd557ff00..000000000 --- a/litex/build/sim/core/modules/ethernet/tapcfg +++ /dev/null @@ -1 +0,0 @@ -Subproject commit bd557ff00d8fe2473fcf346e36c96d004e94b8ca diff --git a/litex/soc/cores/cpu/blackparrot/pre-alpha-release b/litex/soc/cores/cpu/blackparrot/pre-alpha-release deleted file mode 160000 index dbb13f313..000000000 --- a/litex/soc/cores/cpu/blackparrot/pre-alpha-release +++ /dev/null @@ -1 +0,0 @@ -Subproject commit dbb13f31370a743633dc94d3639d55c8c4d74e1d diff --git a/litex/soc/cores/cpu/lm32/verilog/submodule b/litex/soc/cores/cpu/lm32/verilog/submodule deleted file mode 160000 index 84b3e3ca0..000000000 --- a/litex/soc/cores/cpu/lm32/verilog/submodule +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 84b3e3ca0ad9535acaef201c1482342871358b08 diff --git a/litex/soc/cores/cpu/microwatt/sources b/litex/soc/cores/cpu/microwatt/sources deleted file mode 160000 index 1a826f077..000000000 --- a/litex/soc/cores/cpu/microwatt/sources +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 1a826f077bb518bc3ffd799c47a6dd2852165f89 diff --git a/litex/soc/cores/cpu/minerva/verilog b/litex/soc/cores/cpu/minerva/verilog deleted file mode 160000 index fb296e4e4..000000000 --- a/litex/soc/cores/cpu/minerva/verilog +++ /dev/null @@ -1 +0,0 @@ -Subproject commit fb296e4e48e5ced8dd05f2228d84b4bc18f54f75 diff --git a/litex/soc/cores/cpu/mor1kx/verilog b/litex/soc/cores/cpu/mor1kx/verilog deleted file mode 160000 index 69b97fcb4..000000000 --- a/litex/soc/cores/cpu/mor1kx/verilog +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 69b97fcb43b35d6c6639ecc68e63d912c09ee8da diff --git a/litex/soc/cores/cpu/picorv32/verilog b/litex/soc/cores/cpu/picorv32/verilog deleted file mode 160000 index a9e0ea54c..000000000 --- a/litex/soc/cores/cpu/picorv32/verilog +++ /dev/null @@ -1 +0,0 @@ -Subproject commit a9e0ea54cffa162cfe901ff8d30d8877a18c6d8e diff --git a/litex/soc/cores/cpu/rocket/verilog b/litex/soc/cores/cpu/rocket/verilog deleted file mode 160000 index fb31001d9..000000000 --- a/litex/soc/cores/cpu/rocket/verilog +++ /dev/null @@ -1 +0,0 @@ -Subproject commit fb31001d9655ebfb8ab25209e094939f68feb6a7 diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog deleted file mode 160000 index 8baad2198..000000000 --- a/litex/soc/cores/cpu/vexriscv/verilog +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 8baad219885a47f65959a9cd4870691e84678db4 diff --git a/litex/soc/software/compiler_rt b/litex/soc/software/compiler_rt deleted file mode 160000 index 81fb4f00c..000000000 --- a/litex/soc/software/compiler_rt +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 81fb4f00c2cfe13814765968e09931ffa93b5138 From 83b25813311ce63edd8434500a0d3872967baca7 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 23 Feb 2020 17:04:47 -0800 Subject: [PATCH 10/16] Fix the libcompiler_rt path. --- litex/soc/integration/builder.py | 3 +++ litex/soc/software/libcompiler_rt/Makefile | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/litex/soc/integration/builder.py b/litex/soc/integration/builder.py index 6e995fa4c..80cc3753a 100644 --- a/litex/soc/integration/builder.py +++ b/litex/soc/integration/builder.py @@ -15,6 +15,7 @@ import struct import shutil from litex.build.tools import write_to_file +from litex.data.find import find_data from litex.soc.integration import export, soc_core __all__ = ["soc_software_packages", "soc_directory", @@ -100,6 +101,8 @@ class Builder: exec_profiles["EXECUTE_IN_PLACE"] = "1" for k, v in exec_profiles.items(): define(k, v) + define( + "COMPILER_RT_DIRECTORY", find_data("software", "compiler_rt")) define("SOC_DIRECTORY", soc_directory) variables_contents.append("export BUILDINC_DIRECTORY\n") define("BUILDINC_DIRECTORY", self.include_dir) diff --git a/litex/soc/software/libcompiler_rt/Makefile b/litex/soc/software/libcompiler_rt/Makefile index 929616b3c..ef78cd569 100644 --- a/litex/soc/software/libcompiler_rt/Makefile +++ b/litex/soc/software/libcompiler_rt/Makefile @@ -23,7 +23,7 @@ libcompiler_rt.a: $(OBJECTS) mulsi3.o: $(SOC_DIRECTORY)/software/libcompiler_rt/mulsi3.c $(compile) -%.o: $(SOC_DIRECTORY)/software/compiler_rt/lib/builtins/%.c +%.o: $(COMPILER_RT_DIRECTORY)/lib/builtins/%.c $(compile) .PHONY: all clean From 2e3b7f20c79b331072e2e6cca9dbf43cdcdaa93d Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 29 Mar 2020 17:28:20 -0700 Subject: [PATCH 11/16] Fix typo in error message. --- litex/data/find.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex/data/find.py b/litex/data/find.py index 1a143b1dc..74c910992 100644 --- a/litex/data/find.py +++ b/litex/data/find.py @@ -7,7 +7,7 @@ def find_data(data_type, data_name): return dm.data_location except ImportError as e: raise ImportError("""\ -litex-data-{dt}-{dn} module not install! Unable to use {dn} {dt}. +litex-data-{dt}-{dn} module not installed! Unable to use {dn} {dt}. {e} You can install this by running; From e618d41ffb69000662693b1515b3e0a4549780b7 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 29 Mar 2020 17:28:46 -0700 Subject: [PATCH 12/16] Fixing mor1kx data finding. --- litex/soc/cores/cpu/mor1kx/core.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index 4fe41b36c..a380e3faf 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -174,8 +174,7 @@ class MOR1KX(CPU): @staticmethod def add_sources(platform): vdir = os.path.join( - os.path.abspath(os.path.dirname(__file__)), - "verilog", "rtl", "verilog") + find_data("cpu", "mor1kx"), "rtl", "verilog") platform.add_source_dir(vdir) platform.add_verilog_include_path(vdir) From a39a4ec2ed9657c6f34285f28e6dffd88ee49046 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sun, 29 Mar 2020 17:36:06 -0700 Subject: [PATCH 13/16] Only allow fast-forward pulls. --- litex_setup.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_setup.py b/litex_setup.py index c6389ad66..be9c3b432 100755 --- a/litex_setup.py +++ b/litex_setup.py @@ -136,7 +136,7 @@ if "update" in sys.argv[1:]: print("[updating " + name + "]...") os.chdir(os.path.join(current_path, name)) subprocess.check_call( - "git pull", + "git pull --ff-only", shell=True) os.chdir(os.path.join(current_path)) From ebcb2a44064f5a09668c18d7f9d66ca4e85063b5 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Mon, 6 Apr 2020 11:16:57 -0700 Subject: [PATCH 14/16] Rename litex-data-XXX-YYY to pythondata-XXX-YYY --- litex/__init__.py | 20 +++++++++++++++++--- litex/data/__init__.py | 2 -- litex/data/find.py | 15 --------------- litex/soc/cores/cpu/blackparrot/core.py | 5 +++-- litex/soc/cores/cpu/lm32/core.py | 4 ++-- litex/soc/cores/cpu/microwatt/core.py | 6 ++++-- litex/soc/cores/cpu/mor1kx/core.py | 5 +++-- litex/soc/cores/cpu/picorv32/core.py | 4 ++-- litex/soc/cores/cpu/rocket/core.py | 4 ++-- litex/soc/cores/cpu/vexriscv/core.py | 4 ++-- litex/soc/integration/builder.py | 5 +++-- litex_setup.py | 18 +++++++++--------- setup.py | 2 +- 13 files changed, 48 insertions(+), 46 deletions(-) delete mode 100644 litex/data/__init__.py delete mode 100644 litex/data/find.py diff --git a/litex/__init__.py b/litex/__init__.py index 2454c0e79..0499e31a8 100644 --- a/litex/__init__.py +++ b/litex/__init__.py @@ -1,6 +1,3 @@ -# https://packaging.python.org/guides/packaging-namespace-packages/#pkgutil-style-namespace-packages -__path__ = __import__('pkgutil').extend_path(__path__, __name__) - import sys # retro-compat 2019-09-30 @@ -12,3 +9,20 @@ from litex.soc.integration import export sys.modules["litex.soc.integration.cpu_interface"] = export from litex.tools.litex_client import RemoteClient + +def get_data_mod(data_type, data_name): + """Get the pythondata-{}-{} module or raise a useful error message.""" + imp = "import pythondata_{}_{} as dm".format(data_type, data_name) + try: + l = {} + exec(imp, {}, l) + dm = l['dm'] + return dm + except ImportError as e: + raise ImportError("""\ +pythondata-{dt}-{dn} module not installed! Unable to use {dn} {dt}. +{e} + +You can install this by running; + pip install git+https://github.com/litex-hub/pythondata-{dt}-{dn}.git +""".format(dt=data_type, dn=data_name, e=e)) diff --git a/litex/data/__init__.py b/litex/data/__init__.py deleted file mode 100644 index c9b5ae908..000000000 --- a/litex/data/__init__.py +++ /dev/null @@ -1,2 +0,0 @@ -# https://packaging.python.org/guides/packaging-namespace-packages/#pkgutil-style-namespace-packages -__path__ = __import__('pkgutil').extend_path(__path__, __name__) diff --git a/litex/data/find.py b/litex/data/find.py deleted file mode 100644 index 74c910992..000000000 --- a/litex/data/find.py +++ /dev/null @@ -1,15 +0,0 @@ -def find_data(data_type, data_name): - imp = "from litex.data.{} import {} as dm".format(data_type, data_name) - try: - l = {} - exec(imp, {}, l) - dm = l['dm'] - return dm.data_location - except ImportError as e: - raise ImportError("""\ -litex-data-{dt}-{dn} module not installed! Unable to use {dn} {dt}. -{e} - -You can install this by running; - pip install git+https://github.com/litex-hub/litex-data-{dt}-{dn}.git -""".format(dt=data_type, dn=data_name, e=e)) diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py index e55e6252b..9f61c6c69 100644 --- a/litex/soc/cores/cpu/blackparrot/core.py +++ b/litex/soc/cores/cpu/blackparrot/core.py @@ -32,7 +32,7 @@ import os from migen import * -from litex.data.find import find_data +from litex import get_data_mod from litex.soc.interconnect import axi from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -116,7 +116,8 @@ class BlackParrotRV64(CPU): @staticmethod def add_sources(platform, variant="standard"): - filename = os.path.join(find_data("cpu", "blackparrot"), "flist_litex.verilator") + filename = get_data_mod("cpu", "blackparrot").data_file( + "flist_litex.verilator") with open(filename) as openfileobject: for line in openfileobject: temp = line diff --git a/litex/soc/cores/cpu/lm32/core.py b/litex/soc/cores/cpu/lm32/core.py index 75e7ba8cb..ffa910d01 100644 --- a/litex/soc/cores/cpu/lm32/core.py +++ b/litex/soc/cores/cpu/lm32/core.py @@ -9,7 +9,7 @@ import os from migen import * -from litex.data.find import find_data +from litex import get_data_mod from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -97,7 +97,7 @@ class LM32(CPU): @staticmethod def add_sources(platform, variant): - vdir = find_data("cpu", "lm32") + vdir = get_data_mod("cpu", "lm32").data_location platform.add_sources(os.path.join(vdir, "rtl"), "lm32_cpu.v", "lm32_instruction_unit.v", diff --git a/litex/soc/cores/cpu/microwatt/core.py b/litex/soc/cores/cpu/microwatt/core.py index aa00ee172..d918d8b13 100644 --- a/litex/soc/cores/cpu/microwatt/core.py +++ b/litex/soc/cores/cpu/microwatt/core.py @@ -6,7 +6,7 @@ import os from migen import * -from litex.data.find import find_data +from litex import get_data_mod from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -99,7 +99,9 @@ class Microwatt(CPU): @staticmethod def add_sources(platform): - sdir = os.path.join(find_data("cpu", "microwatt"), "sources") + sdir = os.path.join( + get_data_mod("cpu", "microwatt").data_location, + "sources") platform.add_sources(sdir, # Common / Types / Helpers "decode_types.vhdl", diff --git a/litex/soc/cores/cpu/mor1kx/core.py b/litex/soc/cores/cpu/mor1kx/core.py index a380e3faf..7c3d86a9b 100644 --- a/litex/soc/cores/cpu/mor1kx/core.py +++ b/litex/soc/cores/cpu/mor1kx/core.py @@ -8,7 +8,7 @@ import os from migen import * -from litex.data.find import find_data +from litex import get_data_mod from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -174,7 +174,8 @@ class MOR1KX(CPU): @staticmethod def add_sources(platform): vdir = os.path.join( - find_data("cpu", "mor1kx"), "rtl", "verilog") + get_data_mod("cpu", "mor1kx").data_location, + "rtl", "verilog") platform.add_source_dir(vdir) platform.add_verilog_include_path(vdir) diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index 47017ac6b..b798e9dd7 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -11,7 +11,7 @@ import os from migen import * -from litex.data.find import find_data +from litex import get_data_mod from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -180,7 +180,7 @@ class PicoRV32(CPU): @staticmethod def add_sources(platform): - vdir = find_data("cpu", "picorv32") + vdir = get_data_mod("cpu", "picorv32").data_location platform.add_source(os.path.join(vdir, "picorv32.v")) def do_finalize(self): diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py index dff3fe707..c29a2796b 100644 --- a/litex/soc/cores/cpu/rocket/core.py +++ b/litex/soc/cores/cpu/rocket/core.py @@ -33,7 +33,7 @@ import os from migen import * -from litex.data.find import find_data +from litex import get_data_mod from litex.soc.interconnect import axi from litex.soc.interconnect import wishbone from litex.soc.cores.cpu import CPU @@ -239,7 +239,7 @@ class RocketRV64(CPU): @staticmethod def add_sources(platform, variant="standard"): - vdir = find_data("cpu", "rocket") + vdir = get_data_mod("cpu", "rocket").data_location platform.add_sources( os.path.join(vdir, "generated-src"), CPU_VARIANTS[variant] + ".v", diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 42328d199..157b948a3 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -12,7 +12,7 @@ import os from migen import * -from litex.data.find import find_data +from litex import get_data_mod from litex.soc.interconnect import wishbone from litex.soc.interconnect.csr import * from litex.soc.cores.cpu import CPU @@ -247,7 +247,7 @@ class VexRiscv(CPU, AutoCSR): @staticmethod def add_sources(platform, variant="standard"): cpu_filename = CPU_VARIANTS[variant] + ".v" - vdir = find_data("cpu", "vexriscv") + vdir = get_data_mod("cpu", "vexriscv").data_location platform.add_source(os.path.join(vdir, cpu_filename)) def use_external_variant(self, variant_filename): diff --git a/litex/soc/integration/builder.py b/litex/soc/integration/builder.py index 80cc3753a..745eb75e9 100644 --- a/litex/soc/integration/builder.py +++ b/litex/soc/integration/builder.py @@ -14,8 +14,8 @@ import subprocess import struct import shutil +from litex import get_data_mod from litex.build.tools import write_to_file -from litex.data.find import find_data from litex.soc.integration import export, soc_core __all__ = ["soc_software_packages", "soc_directory", @@ -102,7 +102,8 @@ class Builder: for k, v in exec_profiles.items(): define(k, v) define( - "COMPILER_RT_DIRECTORY", find_data("software", "compiler_rt")) + "COMPILER_RT_DIRECTORY", + get_data_mod("software", "compiler_rt").data_location) define("SOC_DIRECTORY", soc_directory) variables_contents.append("export BUILDINC_DIRECTORY\n") define("BUILDINC_DIRECTORY", self.include_dir) diff --git a/litex_setup.py b/litex_setup.py index be9c3b432..82259f1a1 100755 --- a/litex_setup.py +++ b/litex_setup.py @@ -19,7 +19,7 @@ repos = [ ("migen", ("https://github.com/m-labs/", True, True)), # LiteX SoC builder - ('litex-data-software-compiler_rt', ("https://github.com/litex-hub/", False, True)), + ("pythondata-software-compiler_rt", ("https://github.com/litex-hub/", False, True)), ("litex", ("https://github.com/enjoy-digital/", False, True)), # LiteX cores ecosystem @@ -38,14 +38,14 @@ repos = [ ("litex-boards", ("https://github.com/litex-hub/", False, True)), # Optional LiteX data - ("litex-data-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)), - ("litex-data-cpu-mor1kx", ("https://github.com/litex-hub/", False, True)), - ("litex-data-cpu-lm32", ("https://github.com/litex-hub/", False, True)), - ("litex-data-cpu-microwatt", ("https://github.com/litex-hub/", False, True)), - ("litex-data-cpu-picorv32", ("https://github.com/litex-hub/", False, True)), - ("litex-data-cpu-rocket", ("https://github.com/litex-hub/", False, True)), - ("litex-data-cpu-vexriscv", ("https://github.com/litex-hub/", False, True)), - ("litex-data-misc-tapcfg", ("https://github.com/litex-hub/", False, True)), + ("pythondata-cpu-blackparrot", ("https://github.com/litex-hub/", False, True)), + ("pythondata-cpu-mor1kx", ("https://github.com/litex-hub/", False, True)), + ("pythondata-cpu-lm32", ("https://github.com/litex-hub/", False, True)), + ("pythondata-cpu-microwatt", ("https://github.com/litex-hub/", False, True)), + ("pythondata-cpu-picorv32", ("https://github.com/litex-hub/", False, True)), + ("pythondata-cpu-rocket", ("https://github.com/litex-hub/", False, True)), + ("pythondata-cpu-vexriscv", ("https://github.com/litex-hub/", False, True)), + ("pythondata-misc-tapcfg", ("https://github.com/litex-hub/", False, True)), ] repos = OrderedDict(repos) diff --git a/setup.py b/setup.py index 9c7444270..496c65d64 100755 --- a/setup.py +++ b/setup.py @@ -17,7 +17,7 @@ setup( install_requires=[ "migen", "pyserial", - "litex-data-software-compiler_rt", + "pythondata-software-compiler_rt", ], packages=find_packages(exclude=("test*", "sim*", "doc*")), include_package_data=True, From 3aee8a5227e20e37fef29936b3634360e48264ce Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Wed, 8 Apr 2020 23:17:41 -0700 Subject: [PATCH 15/16] Remove directories from submodules from MANIFEST.in file. --- MANIFEST.in | 7 ------- 1 file changed, 7 deletions(-) diff --git a/MANIFEST.in b/MANIFEST.in index a15c845d9..d64974bd3 100644 --- a/MANIFEST.in +++ b/MANIFEST.in @@ -1,8 +1 @@ graft litex/build/sim -graft litex/soc/software -graft litex/soc/cores/cpu/lm32/verilog -graft litex/soc/cores/cpu/minerva/verilog -graft litex/soc/cores/cpu/mor1kx/verilog -graft litex/soc/cores/cpu/picorv32/verilog -graft litex/soc/cores/cpu/rocket/verilog -graft litex/soc/cores/cpu/vexriscv/verilog From 1f35669508ea1f5fce78e213e44db0ea3e2db805 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Sat, 11 Apr 2020 18:34:29 -0700 Subject: [PATCH 16/16] litex_sim: Find tapcfg from pythondata module. --- litex/build/sim/core/modules/ethernet/Makefile | 6 +++--- litex/build/sim/core/modules/xgmii_ethernet/Makefile | 6 +++--- litex/build/sim/core/modules/xgmii_ethernet/tapcfg | 1 - litex/build/sim/verilator.py | 6 ++++-- 4 files changed, 10 insertions(+), 9 deletions(-) delete mode 120000 litex/build/sim/core/modules/xgmii_ethernet/tapcfg diff --git a/litex/build/sim/core/modules/ethernet/Makefile b/litex/build/sim/core/modules/ethernet/Makefile index 461ed86be..392ede182 100644 --- a/litex/build/sim/core/modules/ethernet/Makefile +++ b/litex/build/sim/core/modules/ethernet/Makefile @@ -3,7 +3,7 @@ UNAME_S := $(shell uname -s) include $(SRC_DIR)/modules/rules.mak -CFLAGS += -I$(MOD_SRC_DIR)/tapcfg/src/include +CFLAGS += -I$(TAPCFG_DIRECTORY)/src/include OBJS = $(MOD).o tapcfg.o taplog.o $(MOD).so: $(OBJS) @@ -13,8 +13,8 @@ else $(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $^ endif -tapcfg.o: $(MOD_SRC_DIR)/tapcfg/src/lib/tapcfg.c +tapcfg.o: $(TAPCFG_DIRECTORY)/src/lib/tapcfg.c $(CC) $(CFLAGS) -c -o $@ $< -taplog.o: $(MOD_SRC_DIR)/tapcfg/src/lib/taplog.c +taplog.o: $(TAPCFG_DIRECTORY)/src/lib/taplog.c $(CC) $(CFLAGS) -c -o $@ $< diff --git a/litex/build/sim/core/modules/xgmii_ethernet/Makefile b/litex/build/sim/core/modules/xgmii_ethernet/Makefile index 461ed86be..392ede182 100644 --- a/litex/build/sim/core/modules/xgmii_ethernet/Makefile +++ b/litex/build/sim/core/modules/xgmii_ethernet/Makefile @@ -3,7 +3,7 @@ UNAME_S := $(shell uname -s) include $(SRC_DIR)/modules/rules.mak -CFLAGS += -I$(MOD_SRC_DIR)/tapcfg/src/include +CFLAGS += -I$(TAPCFG_DIRECTORY)/src/include OBJS = $(MOD).o tapcfg.o taplog.o $(MOD).so: $(OBJS) @@ -13,8 +13,8 @@ else $(CC) $(LDFLAGS) -Wl,-soname,$@ -o $@ $^ endif -tapcfg.o: $(MOD_SRC_DIR)/tapcfg/src/lib/tapcfg.c +tapcfg.o: $(TAPCFG_DIRECTORY)/src/lib/tapcfg.c $(CC) $(CFLAGS) -c -o $@ $< -taplog.o: $(MOD_SRC_DIR)/tapcfg/src/lib/taplog.c +taplog.o: $(TAPCFG_DIRECTORY)/src/lib/taplog.c $(CC) $(CFLAGS) -c -o $@ $< diff --git a/litex/build/sim/core/modules/xgmii_ethernet/tapcfg b/litex/build/sim/core/modules/xgmii_ethernet/tapcfg deleted file mode 120000 index d0b6901bd..000000000 --- a/litex/build/sim/core/modules/xgmii_ethernet/tapcfg +++ /dev/null @@ -1 +0,0 @@ -../ethernet/tapcfg/ \ No newline at end of file diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py index f068d08d1..2fc251940 100644 --- a/litex/build/sim/verilator.py +++ b/litex/build/sim/verilator.py @@ -7,7 +7,7 @@ import sys import subprocess from migen.fhdl.structure import _Fragment - +from litex import get_data_mod from litex.build import tools from litex.build.generic_platform import * @@ -102,13 +102,15 @@ extern "C" void litex_sim_init(void **out) def _generate_sim_variables(include_paths): + tapcfg_dir = get_data_mod("misc", "tapcfg").data_location include = "" for path in include_paths: include += "-I"+path+" " content = """\ SRC_DIR = {} INC_DIR = {} -""".format(core_directory, include) +TAPCFG_DIRECTORY = {} +""".format(core_directory, include, tapcfg_dir) tools.write_to_file("variables.mak", content)