From 4dabf0a330fd2454c1f9db4c9c978aa2bd754b5f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 24 Mar 2023 09:02:49 +0100 Subject: [PATCH] cpu/vexriscv/naxriscv: Use reserved_interrupts to reserved interrupt 0. --- litex/soc/cores/cpu/naxriscv/core.py | 8 ++++---- litex/soc/cores/cpu/vexriscv_smp/core.py | 9 +++++---- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/litex/soc/cores/cpu/naxriscv/core.py b/litex/soc/cores/cpu/naxriscv/core.py index 46958ea47..56052b874 100755 --- a/litex/soc/cores/cpu/naxriscv/core.py +++ b/litex/soc/cores/cpu/naxriscv/core.py @@ -91,6 +91,10 @@ class NaxRiscv(CPU): flags += f" -DUART_POLLING" return flags + # Reserved Interrupts. + @property + def reserved_interrupts(self): + return {"noirq": 0} # Command line configuration arguments. @staticmethod @@ -181,10 +185,6 @@ class NaxRiscv(CPU): i_peripheral_dbus_rresp = dbus.r.resp, ) - # IRQs (Note: 0 is reserved as a "No IRQ"). - self.interrupts.update({"uart" : 1}) - self.interrupts.update({"timer0" : 2}) - def set_reset_address(self, reset_address): self.reset_address = reset_address diff --git a/litex/soc/cores/cpu/vexriscv_smp/core.py b/litex/soc/cores/cpu/vexriscv_smp/core.py index b4fe21734..9b48c79f8 100755 --- a/litex/soc/cores/cpu/vexriscv_smp/core.py +++ b/litex/soc/cores/cpu/vexriscv_smp/core.py @@ -150,6 +150,11 @@ class VexRiscvSMP(CPU): flags += f" -DUART_POLLING" return flags + # Reserved Interrupts. + @property + def reserved_interrupts(self): + return {"noirq": 0} + # Cluster Name Generation. @staticmethod def generate_cluster_name(): @@ -356,10 +361,6 @@ class VexRiscvSMP(CPU): ) ] - # IRQs (Note: 0 is reserved as a "No IRQ"). - self.interrupts.update({"uart" : 1}) - self.interrupts.update({"timer0" : 2}) - def set_reset_address(self, reset_address): self.reset_address = reset_address assert reset_address == 0x0000_0000