From 4dccb8a9eb305d52d30e9c2e563d1b814a6585a5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 1 May 2019 12:58:44 +0200 Subject: [PATCH] soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent --- litex/soc/interconnect/axi.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py index 75163cbcf..324f28743 100644 --- a/litex/soc/interconnect/axi.py +++ b/litex/soc/interconnect/axi.py @@ -122,10 +122,12 @@ class AXI2Wishbone(Module): assert axi.data_width == len(wishbone.dat_r) assert axi.address_width == len(wishbone.adr) + 2 + ax_buffer = stream.Buffer(ax_description(axi.address_width, axi.id_width)) ax_burst = stream.Endpoint(ax_description(axi.address_width, axi.id_width)) ax_beat = stream.Endpoint(ax_description(axi.address_width, axi.id_width)) - ax_burst2beat = AXIBurst2Beat(ax_burst, ax_beat) - self.submodules += ax_burst2beat + self.comb += ax_burst.connect(ax_buffer.sink) + ax_burst2beat = AXIBurst2Beat(ax_buffer.source, ax_beat) + self.submodules += ax_buffer, ax_burst2beat _data = Signal(axi.data_width) _addr = Signal(axi.address_width)