diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 6760db75e..0b73ddf66 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1530,7 +1530,7 @@ class LiteXSoC(SoC):
         self.check_if_exists(name)
         etherbone = LiteEthEtherbone(ethcore.udp, udp_port, buffer_depth=buffer_depth, cd=name)
         setattr(self.submodules, name, etherbone)
-        self.add_wb_master(etherbone.wishbone.bus)
+        self.bus.add_master(master=etherbone.wishbone.bus)
 
         # Timing constraints
         if with_timing_constraints:
@@ -1753,8 +1753,8 @@ class LiteXSoC(SoC):
         # MMAP.
         self.check_if_exists(f"{name}_mmap")
         mmap = LitePCIeWishboneMaster(self.pcie_endpoint, base_address=self.mem_map["csr"])
-        self.add_wb_master(mmap.wishbone)
         setattr(self.submodules, f"{name}_mmap", mmap)
+        self.bus.add_master(master=mmap.wishbone)
 
         # MSI.
         if with_msi:
diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index fed0286d7..db6204cac 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -233,7 +233,7 @@ class SimSoC(SoCCore):
             self.submodules.udp  = LiteEthUDP(self.ip, etherbone_ip_address, dw=8)
             # Etherbone
             self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master")
-            self.add_wb_master(self.etherbone.wishbone.bus)
+            self.bus.add_master(master=self.etherbone.wishbone.bus)
 
         # Ethernet ---------------------------------------------------------------------------------
         elif with_ethernet: