From 4dece4ce24972fb2652ee6183bed1cec9ab40672 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 27 Apr 2020 19:06:16 +0200 Subject: [PATCH] soc/cpu: simplify integration of CPU without interrupts (and automatically use UART_POLLING mode in this case). --- litex/soc/cores/cpu/serv/core.py | 1 - litex/soc/integration/soc.py | 16 +++++++++++----- litex/soc/integration/soc_core.py | 3 --- litex/soc/software/bios/boot.c | 3 +++ litex/soc/software/bios/isr.c | 14 ++++++++++---- litex/soc/software/bios/main.c | 3 ++- litex/soc/software/include/base/irq.h | 25 +++++-------------------- 7 files changed, 31 insertions(+), 34 deletions(-) diff --git a/litex/soc/cores/cpu/serv/core.py b/litex/soc/cores/cpu/serv/core.py index c919fb532..4fb2f0a49 100644 --- a/litex/soc/cores/cpu/serv/core.py +++ b/litex/soc/cores/cpu/serv/core.py @@ -37,7 +37,6 @@ class SERV(CPU): self.ibus = ibus = wishbone.Interface() self.dbus = dbus = wishbone.Interface() self.buses = [ibus, dbus] - self.interrupt = Signal(32) # # # diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index b06abdef7..dcea829aa 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -723,7 +723,7 @@ class SoC(Module): raise self.constants[name] = SoCConstant(value) - def add_config(self, name, value): + def add_config(self, name, value=None): name = "CONFIG_" + name if isinstance(value, str): self.add_constant(name + "_" + value) @@ -784,8 +784,10 @@ class SoC(Module): for n, cpu_bus in enumerate(self.cpu.buses): self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus) self.csr.add("cpu", use_loc_if_exists=True) - for name, loc in self.cpu.interrupts.items(): - self.irq.add(name, loc) + if hasattr(self.cpu, "interrupt"): + for name, loc in self.cpu.interrupts.items(): + self.irq.add(name, loc) + self.add_config("CPU_HAS_INTERRUPT") if hasattr(self, "ctrl"): self.comb += self.cpu.reset.eq(self.ctrl.reset) self.add_config("CPU_RESET_ADDR", reset_address) @@ -797,7 +799,8 @@ class SoC(Module): self.check_if_exists(name) setattr(self.submodules, name, Timer()) self.csr.add(name, use_loc_if_exists=True) - self.irq.add(name, use_loc_if_exists=True) + if hasattr(self.cpu, "interrupt"): + self.irq.add(name, use_loc_if_exists=True) # SoC finalization ----------------------------------------------------------------------------- def do_finalize(self): @@ -974,7 +977,10 @@ class LiteXSoC(SoC): self.csr.add("uart_phy", use_loc_if_exists=True) self.csr.add("uart", use_loc_if_exists=True) - self.irq.add("uart", use_loc_if_exists=True) + if hasattr(self.cpu, "interrupt"): + self.irq.add("uart", use_loc_if_exists=True) + else: + self.add_constant("UART_POLLING") # Add SDRAM ------------------------------------------------------------------------------------ def add_sdram(self, name, phy, module, origin, size=None, diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index ab8704ced..3eb0016c7 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -132,9 +132,6 @@ class SoCCore(LiteXSoC): self.cpu_type = cpu_type self.cpu_variant = cpu_variant - if cpu_type == "serv": - self.add_constant("UART_POLLING") # FIXME: use UART in polling mode for SERV bringup - self.integrated_rom_size = integrated_rom_size self.integrated_rom_initialized = integrated_rom_init != [] self.integrated_sram_size = integrated_sram_size diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c index c6c8b9583..08b3be4a8 100644 --- a/litex/soc/software/bios/boot.c +++ b/litex/soc/software/bios/boot.c @@ -18,6 +18,7 @@ #include #include +#include #ifdef CSR_ETHMAC_BASE #include @@ -38,8 +39,10 @@ static void __attribute__((noreturn)) boot(unsigned long r1, unsigned long r2, u printf("Executing booted program at 0x%08x\n\n", addr); printf("--============= \e[1mLiftoff!\e[0m ===============--\n"); uart_sync(); +#ifdef CONFIG_CPU_HAS_INTERRUPT irq_setmask(0); irq_setie(0); +#endif /* FIXME: understand why flushing icache on Vexriscv make boot fail */ #ifndef __vexriscv__ flush_cpu_icache(); diff --git a/litex/soc/software/bios/isr.c b/litex/soc/software/bios/isr.c index f33cdac43..0044f3d16 100644 --- a/litex/soc/software/bios/isr.c +++ b/litex/soc/software/bios/isr.c @@ -4,14 +4,16 @@ #include +#include #include #include #include +void isr(void); + +#ifdef CONFIG_CPU_HAS_INTERRUPT #if defined(__blackparrot__) /*TODO: Update this function for BP*/ // - -void isr(void); void isr(void) { static int onetime = 0; @@ -36,7 +38,6 @@ void plic_init(void) *((unsigned int *)PLIC_THRSHLD) = 0; } -void isr(void); void isr(void) { unsigned int claim; @@ -62,7 +63,6 @@ void isr(void) } } #else -void isr(void); void isr(void) { __attribute__((unused)) unsigned int irqs; @@ -75,3 +75,9 @@ void isr(void) #endif } #endif + +#else + +void isr(void){}; + +#endif diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c index 08fc6faa9..b6501edbb 100644 --- a/litex/soc/software/bios/main.c +++ b/litex/soc/software/bios/main.c @@ -616,9 +616,10 @@ int main(int i, char **c) { char buffer[64]; int sdr_ok; - +#ifdef CONFIG_CPU_HAS_INTERRUPT irq_setmask(0); irq_setie(1); +#endif uart_init(); printf("\n"); diff --git a/litex/soc/software/include/base/irq.h b/litex/soc/software/include/base/irq.h index 6a2f73944..9fd8e1805 100644 --- a/litex/soc/software/include/base/irq.h +++ b/litex/soc/software/include/base/irq.h @@ -7,6 +7,9 @@ extern "C" { #include #include +#include + +#ifdef CONFIG_CPU_HAS_INTERRUPT #ifdef __picorv32__ // PicoRV32 has a very limited interrupt support, implemented via custom @@ -71,12 +74,8 @@ static inline unsigned int irq_getie(void) return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; #elif defined (__rocket__) return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; -#elif defined (__microwatt__) - return 0; /* No interrupt support on Microwatt */ #elif defined (__blackparrot__) return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0; /* FIXME */ -#elif defined (__serv__) - return 0; /* No interrupt support on SERV */ #else #error Unsupported architecture #endif @@ -102,12 +101,8 @@ static inline void irq_setie(unsigned int ie) if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); #elif defined (__rocket__) if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); -#elif defined (__microwatt__) - /* No interrupt support on Microwatt */ #elif defined (__blackparrot__) if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE); /* FIXME */ -#elif defined (__serv__) - /* No interrupt support on SERV */ #else #error Unsupported architecture #endif @@ -135,12 +130,8 @@ static inline unsigned int irq_getmask(void) return mask; #elif defined (__rocket__) return *((unsigned int *)PLIC_ENABLED) >> 1; -#elif defined (__microwatt__) - return 0; /* No interrupt support on Microwatt */ #elif defined (__blackparrot__) return 0; /* FIXME */ -#elif defined (__serv__) - return 0; /* No interrupt support on SERV */ #else #error Unsupported architecture #endif @@ -162,12 +153,8 @@ static inline void irq_setmask(unsigned int mask) asm volatile ("csrw %0, %1" :: "i"(CSR_IRQ_MASK), "r"(mask)); #elif defined (__rocket__) *((unsigned int *)PLIC_ENABLED) = mask << 1; -#elif defined (__microwatt__) - /* No interrupt support on Microwatt */ #elif defined (__blackparrot__) /* FIXME */ -#elif defined (__serv__) - /* No interrupt support on SERV */ #else #error Unsupported architecture #endif @@ -193,12 +180,8 @@ static inline unsigned int irq_pending(void) return pending; #elif defined (__rocket__) return *((unsigned int *)PLIC_PENDING) >> 1; -#elif defined (__microwatt__) - return 0; /* No interrupt support on Microwatt */ #elif defined (__blackparrot__) return csr_readl(PLIC_PENDING) >> 1; /* FIXME */ -#elif defined (__serv__) - return 0; /* No interrupt support on SERV */ #else #error Unsupported architecture #endif @@ -208,4 +191,6 @@ static inline unsigned int irq_pending(void) } #endif +#endif + #endif /* __IRQ_H */