From 4e3190120e5a2ddf7af5f407978e177ba97935e1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 22 Jan 2015 21:23:14 +0100 Subject: [PATCH] fix build with upstream Migen/MiSoC --- make.py | 8 +++++++- targets/bist.py | 1 + 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/make.py b/make.py index bcd1a17a3..8d5a44397 100644 --- a/make.py +++ b/make.py @@ -7,6 +7,7 @@ from migen.util.misc import autotype from migen.fhdl import verilog, edif from migen.fhdl.structure import _Fragment from mibuild import tools +from mibuild.xilinx_common import * from misoclib.gensoc import cpuif @@ -136,7 +137,12 @@ BIST: {} if not isinstance(soc, _Fragment): soc = soc.get_fragment() platform.finalize(soc) - src = verilog.convert(soc, ios) + so = { + NoRetiming: XilinxNoRetiming, + MultiReg: XilinxMultiReg, + AsyncResetSynchronizer: XilinxAsyncResetSynchronizer + } + src = verilog.convert(soc, ios, special_overrides=so) tools.write_to_file("build/litesata.v", src) if actions["build-bitstream"]: diff --git a/targets/bist.py b/targets/bist.py index 348498e91..03cf31eda 100644 --- a/targets/bist.py +++ b/targets/bist.py @@ -62,6 +62,7 @@ class GenSoC(Module): interrupt_map = {} cpu_type = None def __init__(self, platform, clk_freq): + self.clk_freq = clk_freq # UART <--> Wishbone bridge self.submodules.uart2wb = UART2Wishbone(platform.request("serial"), clk_freq, baud=921600)