From 4f82a36afdccfd030d26bcb49c6fe1017bfb87c2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 1 Jun 2020 10:01:14 +0200 Subject: [PATCH] soc/software: only keep 32-bit CSR alignment support. 64-bit support was added for 64-bit CPU because of limitation of the hardware on CSR accesses. Now that the Wihhbone2CSR bus handles wishbone.sel, this is no longer required. --- litex/soc/integration/soc.py | 21 ++------------------- litex/soc/integration/soc_core.py | 2 -- litex/soc/software/bios/main.c | 5 ++--- litex/soc/software/include/hw/common.h | 25 ++++--------------------- 4 files changed, 8 insertions(+), 45 deletions(-) diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py index 84ec63d75..f3191e053 100644 --- a/litex/soc/integration/soc.py +++ b/litex/soc/integration/soc.py @@ -437,7 +437,7 @@ class SoCLocHandler(Module): class SoCCSRHandler(SoCLocHandler): supported_data_width = [8, 32] supported_address_width = [14+i for i in range(4)] - supported_alignment = [32, 64] + supported_alignment = [32] supported_paging = [0x800*2**i for i in range(4)] # Creation ------------------------------------------------------------------------------------- @@ -505,21 +505,6 @@ class SoCCSRHandler(SoCLocHandler): self.logger.info("CSR Handler {}.".format(colorer("created", color="green"))) - # Update CSR Alignment ---------------------------------------------------------------------------- - def update_alignment(self, alignment): - # Check Alignment - if alignment not in self.supported_alignment: - self.logger.error("Unsupported {}: {} supporteds: {:s}".format( - colorer("Alignment", color="red"), - colorer(alignment), - colorer(", ".join(str(x) for x in self.supported_alignment)))) - raise - self.logger.info("Alignment {} from {}-bit to {}-bit.".format( - colorer("updated", color="cyan"), - colorer(self.alignment), - colorer(alignment))) - self.alignment = alignment - # Add Master ----------------------------------------------------------------------------------- def add_master(self, name=None, master=None): if name is None: @@ -652,7 +637,6 @@ class SoC(Module): csr_data_width = 32, csr_address_width = 14, - csr_alignment = 32, csr_paging = 0x800, csr_reserved_csrs = {}, @@ -692,7 +676,7 @@ class SoC(Module): self.submodules.csr = SoCCSRHandler( data_width = csr_data_width, address_width = csr_address_width, - alignment = csr_alignment, + alignment = 32, paging = csr_paging, reserved_csrs = csr_reserved_csrs, ) @@ -791,7 +775,6 @@ class SoC(Module): self.mem_map.update(self.cpu.mem_map) # FIXME # Add Bus Masters/CSR/IRQs if not isinstance(self.cpu, cpu.CPUNone): - self.csr.update_alignment(self.cpu.data_width) if reset_address is None: reset_address = self.mem_map["rom"] self.cpu.set_reset_address(reset_address) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 1b90c1ac3..a1ba58624 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -82,7 +82,6 @@ class SoCCore(LiteXSoC): integrated_main_ram_init = [], # CSR parameters csr_data_width = 8, - csr_alignment = 32, csr_address_width = 14, csr_paging = 0x800, # Identifier parameters @@ -111,7 +110,6 @@ class SoCCore(LiteXSoC): csr_data_width = csr_data_width, csr_address_width = csr_address_width, - csr_alignment = csr_alignment, csr_paging = csr_paging, csr_reserved_csrs = self.csr_map, diff --git a/litex/soc/software/bios/main.c b/litex/soc/software/bios/main.c index a7e348d53..f56adff26 100644 --- a/litex/soc/software/bios/main.c +++ b/litex/soc/software/bios/main.c @@ -107,9 +107,8 @@ int main(int i, char **c) CONFIG_BUS_STANDARD, CONFIG_BUS_DATA_WIDTH, (1 << (CONFIG_BUS_ADDRESS_WIDTH - 30))); - printf("\e[1mCSR\e[0m: %d-bit data - %d-bit aligned\n", - CONFIG_CSR_DATA_WIDTH, - CONFIG_CSR_ALIGNMENT); + printf("\e[1mCSR\e[0m: %d-bit data\n", + CONFIG_CSR_DATA_WIDTH); printf("\e[1mROM\e[0m: %dKiB\n", ROM_SIZE/1024); printf("\e[1mSRAM\e[0m: %dKiB\n", SRAM_SIZE/1024); #ifdef CONFIG_L2_SIZE diff --git a/litex/soc/software/include/hw/common.h b/litex/soc/software/include/hw/common.h index b976bd9e0..090253a61 100644 --- a/litex/soc/software/include/hw/common.h +++ b/litex/soc/software/include/hw/common.h @@ -20,30 +20,13 @@ * (base) address. */ #include -#if !defined(CONFIG_CSR_ALIGNMENT) || !defined(CONFIG_CSR_DATA_WIDTH) -#error csr alignment and data-width MUST be set before including this file! +#if !defined(CONFIG_CSR_DATA_WIDTH) +#error CSR_DATA_WIDTH MUST be set before including this file! #endif -#if CONFIG_CSR_DATA_WIDTH > CONFIG_CSR_ALIGNMENT -#error invalid CONFIG_CSR_DATA_WIDTH (must not exceed CONFIG_CSR_ALIGNMENT)! -#endif - -/* FIXME: preprocessor can't evaluate 'sizeof()' operator, is there a better - * way to implement the following assertion? - * #if sizeof(unsigned long) != CONFIG_CSR_ALIGNMENT/8 - * #error invalid CONFIG_CSR_ALIGNMENT (must match native CPU word size)! - * #endif - */ - -/* CSR subregisters (a.k.a. "simple CSRs") are embedded inside native CPU-word +/* CSR subregisters (a.k.a. "simple CSRs") are embedded inside uint32_t * aligned locations: */ -#if CONFIG_CSR_ALIGNMENT == 32 #define MMPTR(a) (*((volatile uint32_t *)(a))) -#elif CONFIG_CSR_ALIGNMENT == 64 -#define MMPTR(a) (*((volatile uint64_t *)(a))) -#else -#error Unsupported CSR alignment -#endif static inline void csr_write_simple(unsigned long v, unsigned long a) { @@ -61,7 +44,7 @@ static inline unsigned long csr_read_simple(unsigned long a) /* CSR data width (subreg. width) in bytes, for direct comparson to sizeof() */ #define CSR_DW_BYTES (CONFIG_CSR_DATA_WIDTH/8) -#define CSR_OFFSET_BYTES (CONFIG_CSR_ALIGNMENT/8) +#define CSR_OFFSET_BYTES 4 #ifndef __ASSEMBLER__