diff --git a/litex/boards/targets/ulx3s.py b/litex/boards/targets/ulx3s.py
index 8ff3777cf..f6794cd67 100755
--- a/litex/boards/targets/ulx3s.py
+++ b/litex/boards/targets/ulx3s.py
@@ -56,7 +56,7 @@ class _CRG(Module):
 
 class BaseSoC(SoCSDRAM):
     def __init__(self, **kwargs):
-        platform = ulx3s.Platform(toolchain="prjtrellis")
+        platform = ulx3s.Platform(toolchain="trellis")
         sys_clk_freq = int(25e6)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
                           l2_size=32,
diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index 1e3e6c70d..eb1bfeffd 100755
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -58,7 +58,7 @@ class _CRG(Module):
 
 class BaseSoC(SoCSDRAM):
     def __init__(self, **kwargs):
-        platform = versa_ecp5.Platform(toolchain="prjtrellis")
+        platform = versa_ecp5.Platform(toolchain="trellis")
         platform.add_extension(versa_ecp5._ecp5_soc_hat_io)
         sys_clk_freq = int(50e6)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,